A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs
In this paper, we have investigated various middle-of-line contact architectures applied to monolithic complementary FET inverters and have performed a comparative analysis to assess their respective advantages and limitations. For each scheme, we carried out segmentation analysis of resistance and...
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2025-01-01
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| author | Seung Kyu Kim Johyeon Kim Gunhee Choi Kee-Won Kwon Jongwook Jeon |
| author_facet | Seung Kyu Kim Johyeon Kim Gunhee Choi Kee-Won Kwon Jongwook Jeon |
| author_sort | Seung Kyu Kim |
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| description | In this paper, we have investigated various middle-of-line contact architectures applied to monolithic complementary FET inverters and have performed a comparative analysis to assess their respective advantages and limitations. For each scheme, we carried out segmentation analysis of resistance and capacitance, and evaluated the DC performance as well as the power-performance characteristics alongside enhancement strategies. The middle VIA scheme features the lowest capacitance but exhibits inferior AC performance to the conventional structure due to the high resistance of the increased contact region parts and the highly doped silicon. The wrap-around-contact (WAC) structure, and the top metal source/drain (TMS) structure which is formed by increasing the contact depth of the top-placed NMOS, have in common that the external resistance is greatly reduced by enlarging the contact area and shortening the length of the high-resistance power VIA. Despite the trade-off with higher capacitance, AC performances of WAC and TMS are improved by 9.0% and 6.5%, respectively, for the same dynamic power. A sensitivity analysis was also performed to clarify the impact of MOL resistance and capacitance on AC performance. The performance gain when applied only to the drain side is less than 1%, highlighting the importance of minimizing the resistance on the source side. In addition, the segmentation analysis of resistance and capacitance shows that while WAC offers the best inverter performance, TMS provides higher DC performance and lower capacitance for NMOS. A hybrid approach using TMS for NMOS and WAC for PMOS combined with further optimization to reduce capacitance on the drain side, would result in an 11.1% speed improvement or a 22.7% reduction in dynamic power consumption. |
| format | Article |
| id | doaj-art-97c6e9a2f1f24d91ba9b8fccf11596b0 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
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| series | IEEE Access |
| spelling | doaj-art-97c6e9a2f1f24d91ba9b8fccf11596b02025-01-10T00:01:30ZengIEEEIEEE Access2169-35362025-01-01135396540510.1109/ACCESS.2024.352343410816635A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETsSeung Kyu Kim0https://orcid.org/0009-0006-9132-2620Johyeon Kim1https://orcid.org/0009-0005-1714-4021Gunhee Choi2Kee-Won Kwon3https://orcid.org/0000-0003-4513-8532Jongwook Jeon4https://orcid.org/0000-0002-5232-650XDepartment of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon-si, South KoreaDepartment of Semiconductor Convergence Engineering, Sungkyunkwan University, Suwon-si, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon-si, South KoreaDepartment of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon-si, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon-si, South KoreaIn this paper, we have investigated various middle-of-line contact architectures applied to monolithic complementary FET inverters and have performed a comparative analysis to assess their respective advantages and limitations. For each scheme, we carried out segmentation analysis of resistance and capacitance, and evaluated the DC performance as well as the power-performance characteristics alongside enhancement strategies. The middle VIA scheme features the lowest capacitance but exhibits inferior AC performance to the conventional structure due to the high resistance of the increased contact region parts and the highly doped silicon. The wrap-around-contact (WAC) structure, and the top metal source/drain (TMS) structure which is formed by increasing the contact depth of the top-placed NMOS, have in common that the external resistance is greatly reduced by enlarging the contact area and shortening the length of the high-resistance power VIA. Despite the trade-off with higher capacitance, AC performances of WAC and TMS are improved by 9.0% and 6.5%, respectively, for the same dynamic power. A sensitivity analysis was also performed to clarify the impact of MOL resistance and capacitance on AC performance. The performance gain when applied only to the drain side is less than 1%, highlighting the importance of minimizing the resistance on the source side. In addition, the segmentation analysis of resistance and capacitance shows that while WAC offers the best inverter performance, TMS provides higher DC performance and lower capacitance for NMOS. A hybrid approach using TMS for NMOS and WAC for PMOS combined with further optimization to reduce capacitance on the drain side, would result in an 11.1% speed improvement or a 22.7% reduction in dynamic power consumption.https://ieeexplore.ieee.org/document/10816635/Complementary FET (CFET)design-technology co-optimization (DTCO)metal source-drainmiddle-of-line (MOL)middle VIA (MV)wrap around contact (WAC) |
| spellingShingle | Seung Kyu Kim Johyeon Kim Gunhee Choi Kee-Won Kwon Jongwook Jeon A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs IEEE Access Complementary FET (CFET) design-technology co-optimization (DTCO) metal source-drain middle-of-line (MOL) middle VIA (MV) wrap around contact (WAC) |
| title | A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs |
| title_full | A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs |
| title_fullStr | A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs |
| title_full_unstemmed | A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs |
| title_short | A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs |
| title_sort | comparative analysis of middle of line contact architectures for complementary fets |
| topic | Complementary FET (CFET) design-technology co-optimization (DTCO) metal source-drain middle-of-line (MOL) middle VIA (MV) wrap around contact (WAC) |
| url | https://ieeexplore.ieee.org/document/10816635/ |
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