FPGA-Based Improved Background Subtraction for Ultra-Low Latency

FPGA-Based Improved Background Subtraction for Ultra-Low Latency

In recent years, advancements in telecommunication technology have led to the proliferation of high-speed, large-capacity, low-latency communication. The COVID-19 pandemic has also accelerated the adoption of remote work globally, making real-time remote communication applications like web conferenc...

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Bibliographic Details
Main Authors: Yoshiyuki Oshima, Yoshiki Yamaguchi, Ryohei Tsugami, Toshihito Fujiwara, Tatsuya Fukui, Satoshi Narikawa
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
FPGA
hardware direct implementation
low-latency
stream processing
background subtraction
background removal
Online Access:https://ieeexplore.ieee.org/document/10721462/
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https://ieeexplore.ieee.org/document/10721462/

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