Design Time Optimization for Hardware Watermarking Protection of HDL Designs

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed hi...

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Bibliographic Details
Main Authors: E. Castillo, D. P. Morales, A. García, L. Parrilla, E. Todorovich, U. Meyer-Baese
Format: Article
Language:English
Published: Wiley 2015-01-01
Series:The Scientific World Journal
Online Access:http://dx.doi.org/10.1155/2015/752969
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