An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI
Recently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves &...
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IEEE
2025-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/10774063/ |
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| author | Bangda Yang Trevor Caldwell Anthony Chan Carusone |
| author_facet | Bangda Yang Trevor Caldwell Anthony Chan Carusone |
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| description | Recently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves −52 dB in total harmonic distortion (THD) through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter (ADC) incorporating the linearized DA in both the input buffer and the first residue amplifier (RA) stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FDSOI) process. Measurements showed the ADC achieved a signal-to-noise-distortion ratio (SNDR) of 37 dB at 920 MS/s consuming a total power of 1.8mW for a Walden FOM (FOMW) of 34.9 fJ/conv. With the input buffer, the achieved FOMW is 68.4 fJ/conv. The linearization technique provided a 8 dB improvement in SNDR at its optimal biasing with a negligible power overhead of approximately 5%. In general, it is expected that an 8 dB SNDR improvement would require 2.5 times the power consumption for a mismatch-limited design (Walden FOM) or 6.3 times the power for a noise-limited design (Schreier FOM). |
| format | Article |
| id | doaj-art-d0a3542fbc974ce98b47e28ec739fd25 |
| institution | Kabale University |
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| publishDate | 2025-01-01 |
| publisher | IEEE |
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| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-d0a3542fbc974ce98b47e28ec739fd252025-01-08T00:01:59ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252025-01-016506210.1109/OJCAS.2024.350974610774063An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOIBangda Yang0https://orcid.org/0009-0000-0057-1004Trevor Caldwell1https://orcid.org/0009-0003-3880-6421Anthony Chan Carusone2https://orcid.org/0000-0002-0977-7516Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, CanadaEdward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, CanadaEdward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, CanadaRecently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves −52 dB in total harmonic distortion (THD) through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter (ADC) incorporating the linearized DA in both the input buffer and the first residue amplifier (RA) stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FDSOI) process. Measurements showed the ADC achieved a signal-to-noise-distortion ratio (SNDR) of 37 dB at 920 MS/s consuming a total power of 1.8mW for a Walden FOM (FOMW) of 34.9 fJ/conv. With the input buffer, the achieved FOMW is 68.4 fJ/conv. The linearization technique provided a 8 dB improvement in SNDR at its optimal biasing with a negligible power overhead of approximately 5%. In general, it is expected that an 8 dB SNDR improvement would require 2.5 times the power consumption for a mismatch-limited design (Walden FOM) or 6.3 times the power for a noise-limited design (Schreier FOM).https://ieeexplore.ieee.org/document/10774063/Analog-to-digital converter (ADC)dynamic amplifierpipelined-SARlinearityfully depleted silicon-on-insulator (FDSOI) |
| spellingShingle | Bangda Yang Trevor Caldwell Anthony Chan Carusone An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI IEEE Open Journal of Circuits and Systems Analog-to-digital converter (ADC) dynamic amplifier pipelined-SAR linearity fully depleted silicon-on-insulator (FDSOI) |
| title | An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI |
| title_full | An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI |
| title_fullStr | An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI |
| title_full_unstemmed | An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI |
| title_short | An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI |
| title_sort | energy efficient pipeline sar adc using linearized dynamic amplifiers and input buffer in 22nm fdsoi |
| topic | Analog-to-digital converter (ADC) dynamic amplifier pipelined-SAR linearity fully depleted silicon-on-insulator (FDSOI) |
| url | https://ieeexplore.ieee.org/document/10774063/ |
| work_keys_str_mv | AT bangdayang anenergyefficientpipelinesaradcusinglinearizeddynamicamplifiersandinputbufferin22nmfdsoi AT trevorcaldwell anenergyefficientpipelinesaradcusinglinearizeddynamicamplifiersandinputbufferin22nmfdsoi AT anthonychancarusone anenergyefficientpipelinesaradcusinglinearizeddynamicamplifiersandinputbufferin22nmfdsoi AT bangdayang energyefficientpipelinesaradcusinglinearizeddynamicamplifiersandinputbufferin22nmfdsoi AT trevorcaldwell energyefficientpipelinesaradcusinglinearizeddynamicamplifiersandinputbufferin22nmfdsoi AT anthonychancarusone energyefficientpipelinesaradcusinglinearizeddynamicamplifiersandinputbufferin22nmfdsoi |