A power‐saving control voltage‐retention circuit for fast‐locking phase‐locked loops with sleep mode
Abstract This study proposes a voltage‐retention circuit (VRC) for a low‐power phase‐locked loop (PLL) designed for mobile interfaces. The PLL, incorporating the proposed scheme, supports the sleep mode to achieve low power consumption and fast switching between the sleep and active modes. To facili...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2024-12-01
|
| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.70118 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|