Charge-trap synaptic device with polycrystalline silicon channel for low power in-memory computing

Charge-trap synaptic device with polycrystalline silicon channel for low power in-memory computing

Abstract Processing-in-memory (PIM) is gaining tremendous research and commercial interest because of its potential to replace the von Neumann bottleneck in current computing architectures. In this study, we implemented a PIM hardware architecture (circuit) based on the charge-trap flash (CTF) as a...

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Bibliographic Details
Main Authors: Min-Kyu Park, Joon Hwang, Soomin Kim, Wonjun Shin, Wonbo Shim, Jong-Ho Bae, Jong-Ho Lee, Seongjae Cho
Format: Article
Language:English
Published: Nature Portfolio 2024-11-01
Series:Scientific Reports
Subjects:
Processing-in-memory (PIM)
Memory wall
Charge-trap flash
poly-Si channel
Inference
Hardware neural network
Online Access:https://doi.org/10.1038/s41598-024-80272-x
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https://doi.org/10.1038/s41598-024-80272-x

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