FPGA IP Core for DC Motor Control With Adaptive Neural Network PID Tuning, and High-Resolution Encoder Interface

FPGA IP Core for DC Motor Control With Adaptive Neural Network PID Tuning, and High-Resolution Encoder Interface

Traditional proportional integral derivative (PID) falls short for precise control of DC motor speed under changing conditions. This paper presents a novel FPGA based IP (intellectual property) core for real-time PID parameter adjustment utilizing a multilayer neural network and the back propagation...

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Bibliographic Details
Main Authors: Naveen C, Sandeep Singh Chauhan, C. Paramasivam, Veerpratap P. Meena
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
FPGA IP
autotuning
proportional integral derivative (PID)
neural network
Online Access:https://ieeexplore.ieee.org/document/10744008/
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https://ieeexplore.ieee.org/document/10744008/

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