Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory Designs
Several 2-D architectures have been presented, including systolic arrays or compute-in-memory (CIM) arrays for energy-efficient artificial intelligence (AI) inference. To increase the energy efficiency within constrained area, 3-D technologies have been actively investigated, which have the potentia...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10714410/ |
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| _version_ | 1841526365940088832 |
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| author | Hyung Joon Byun Udit Gupta Jae-Sun Seo |
| author_facet | Hyung Joon Byun Udit Gupta Jae-Sun Seo |
| author_sort | Hyung Joon Byun |
| collection | DOAJ |
| description | Several 2-D architectures have been presented, including systolic arrays or compute-in-memory (CIM) arrays for energy-efficient artificial intelligence (AI) inference. To increase the energy efficiency within constrained area, 3-D technologies have been actively investigated, which have the potential to decrease the data path length or increase the activation buffer size, enabling higher energy efficiency. Several works have reported the 3-D architectures using non-CIM designs, but investigations on 3-D architectures with CIM macros have not been well studied in prior works. In this article, we investigate digital CIM (DCIM) macros and various 3-D architectures to find the opportunity of increased energy efficiency compared with 2-D structures. Moreover, we also investigated the carbon footprint of 3-D architectures. We have built in-house simulators calculating energy and area given high-level hardware descriptions and DNN workloads and integrated with carbon estimation tool to analyze the embodied carbon of various hardware designs. We have investigated different types of 3-D DCIM architectures and dataflows, which have shown 42.5% energy savings compared with 2-D systolic arrays on average. Also, we have analyzed the tradeoff between performance and carbon footprint and their optimization opportunities. |
| format | Article |
| id | doaj-art-aa4ea8f2cad34eb5a1a55d45f1d59c97 |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-aa4ea8f2cad34eb5a1a55d45f1d59c972025-01-17T00:00:29ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-01109810610.1109/JXCDC.2024.347910010714410Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory DesignsHyung Joon Byun0https://orcid.org/0000-0003-0963-8599Udit Gupta1https://orcid.org/0000-0002-9118-0961Jae-Sun Seo2https://orcid.org/0000-0002-4551-7789Cornell Tech, New York, NY, USACornell Tech, New York, NY, USACornell Tech, New York, NY, USASeveral 2-D architectures have been presented, including systolic arrays or compute-in-memory (CIM) arrays for energy-efficient artificial intelligence (AI) inference. To increase the energy efficiency within constrained area, 3-D technologies have been actively investigated, which have the potential to decrease the data path length or increase the activation buffer size, enabling higher energy efficiency. Several works have reported the 3-D architectures using non-CIM designs, but investigations on 3-D architectures with CIM macros have not been well studied in prior works. In this article, we investigate digital CIM (DCIM) macros and various 3-D architectures to find the opportunity of increased energy efficiency compared with 2-D structures. Moreover, we also investigated the carbon footprint of 3-D architectures. We have built in-house simulators calculating energy and area given high-level hardware descriptions and DNN workloads and integrated with carbon estimation tool to analyze the embodied carbon of various hardware designs. We have investigated different types of 3-D DCIM architectures and dataflows, which have shown 42.5% energy savings compared with 2-D systolic arrays on average. Also, we have analyzed the tradeoff between performance and carbon footprint and their optimization opportunities.https://ieeexplore.ieee.org/document/10714410/3-D integrated circuit (IC)embodied carbonenergy efficiencyperformance analysis |
| spellingShingle | Hyung Joon Byun Udit Gupta Jae-Sun Seo Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory Designs IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3-D integrated circuit (IC) embodied carbon energy efficiency performance analysis |
| title | Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory Designs |
| title_full | Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory Designs |
| title_fullStr | Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory Designs |
| title_full_unstemmed | Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory Designs |
| title_short | Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory Designs |
| title_sort | energy carbon aware evaluation and optimization of 3 d ic architecture with digital compute in memory designs |
| topic | 3-D integrated circuit (IC) embodied carbon energy efficiency performance analysis |
| url | https://ieeexplore.ieee.org/document/10714410/ |
| work_keys_str_mv | AT hyungjoonbyun energycarbonawareevaluationandoptimizationof3dicarchitecturewithdigitalcomputeinmemorydesigns AT uditgupta energycarbonawareevaluationandoptimizationof3dicarchitecturewithdigitalcomputeinmemorydesigns AT jaesunseo energycarbonawareevaluationandoptimizationof3dicarchitecturewithdigitalcomputeinmemorydesigns |