Optimizing Deep Learning Acceleration on FPGA for Real-Time and Resource-Efficient Image Classification

Optimizing Deep Learning Acceleration on FPGA for Real-Time and Resource-Efficient Image Classification

Deep learning (DL) has revolutionized image classification, yet deploying convolutional neural networks (CNNs) on edge devices for real-time applications remains a significant challenge due to constraints in computation, memory, and power efficiency. This work presents an optimized implementation of...

Full description

Saved in:

Bibliographic Details
Main Authors:	Ahmad Mouri Zadeh Khaki, Ahyoung Choi
Format:	Article
Language:	English
Published:	MDPI AG 2025-01-01
Series:	Applied Sciences
Subjects:	AI hardware acceleration convolutional neural network (CNN) deep learning field-programmable gate array (FPGA) transfer learning
Online Access:	https://www.mdpi.com/2076-3417/15/1/422
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Efficient Hardware Implementation of a Multi-Layer Gradient-Free Online-Trainable Spiking Neural Network on FPGA
by: Ali Mehrabi, et al.
Published: (2024-01-01)

An efficient loop tiling framework for convolutional neural network inference accelerators
by: Hongmin Huang, et al.
Published: (2022-01-01)

Accelerating Deep Neural Networks implementation: A survey
by: Meriam Dhouibi, et al.
Published: (2021-03-01)

A Hardware Accelerator for the Inference of a Convolutional Neural network
by: Edwin González, et al.
Published: (2019-11-01)

FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
by: Mustafa Tasci, et al.
Published: (2025-01-01)

Fast approximation of the top‐k items in data streams using FPGAs
by: Ali Ebrahim, et al.
Published: (2023-03-01)

Portable and Cost-Effective Handheld Ultrasound System Utilizing FPGA-Based Synthetic Aperture Imaging
by: Wenping Wang, et al.
Published: (2024-01-01)

FPGA-Based Distributed Union-Find Decoder for Surface Codes
by: Namitha Liyanage, et al.
Published: (2024-01-01)

Survey of FPGA based recurrent neural network accelerator
by: Chen GAO, et al.
Published: (2019-08-01)

Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
by: Mangal D. Gupta, et al.
Published: (2021-09-01)

Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture
by: Xiaoying Huang, et al.
Published: (2021-11-01)

Hardware-accelerated real-time IP flow measurement method for multi-core architecture
by: ZHU Chao1, et al.
Published: (2008-01-01)

Design, Implementation, and Analysis of High-Speed Single-Stage N-Sorters and N-Filters
by: Robert B. Kent, et al.
Published: (2021-01-01)

Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters
by: Robert B. Kent, et al.
Published: (2022-01-01)

Hardware Efficient Speech Enhancement With Noise Aware Multi-Target Deep Learning
by: Salinna Abdullah, et al.
Published: (2024-01-01)

FPGA-Jetson based hardware real-time co-simulation for smart grid
by: Tong DUAN, et al.
Published: (2021-12-01)

CNN Accelerator Performance Dependence on Loop Tiling and the Optimum Resource-Constrained Loop Tiling
by: Chester Sungchung Park, et al.
Published: (2025-01-01)

Accelerating Deep Learning-Based Morphological Biometric Recognition with Field-Programmable Gate Arrays
by: Nourhan Zayed, et al.
Published: (2025-01-01)

FPGA‐based implementation of floating point processing element for the design of efficient FIR filters
by: Tintu Mary John, et al.
Published: (2021-07-01)

Research on Spaceborne Neural Network Accelerator and Its Fault Tolerance Design
by: Yingzhao Shao, et al.
Published: (2024-12-01)

Approximate CNN Hardware Accelerators for Resource Constrained Devices
by: P Thejaswini, et al.
Published: (2025-01-01)

FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing
by: Sayantam Sarkar, et al.
Published: (2021-11-01)

A Pipelined Hardware Design of FNTT and INTT of CRYSTALS-Kyber PQC Algorithm
by: Muhammad Rashid, et al.
Published: (2024-12-01)

Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies
by: Salman Ahmed, et al.
Published: (2025-01-01)

Field-Programmable Gate Array (FPGA)-Based Lock-In Amplifier System with Signal Enhancement: A Comprehensive Review on the Design for Advanced Measurement Applications
by: Jose Alejandro Galaviz-Aguilar, et al.
Published: (2025-01-01)

Sparse Convolution FPGA Accelerator Based on Multi-Bank Hash Selection
by: Jia Xu, et al.
Published: (2024-12-01)

FASQuiC: Flexible Architecture for Scalable Spin Qubit Control
by: Mathieu Toubeix, et al.
Published: (2024-01-01)

Field‐programmable gate array acceleration of the Tersoff potential in LAMMPS
by: Quan Deng, et al.
Published: (2025-01-01)

A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms
by: Umer Farooq, et al.
Published: (2024-12-01)

Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
by: Mountassar Maamoun, et al.
Published: (2021-08-01)

Orchestration mechanism for VNF hardware acceleration resources in SDN/NFV architecture
by: Tong DUAN, et al.
Published: (2018-06-01)

rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA
by: Mohammad Mehdi Rahimifar, et al.
Published: (2025-01-01)

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation
by: Sa'ed Abed, et al.
Published: (2021-03-01)

Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels
by: Ying Zhang, et al.
Published: (2022-01-01)

A Survey on Hardware Accelerators for Large Language Models
by: Christoforos Kachris
Published: (2025-01-01)

Design of an FPGA-Based High-Speed Data Acquisition System for Frequency Scanning Interferometry Long-Range Measurement
by: Sivagunalan Sivanathan, et al.
Published: (2024-01-01)

Implementation of SM3 algorithm based on SoPC component
by: Meng-li SHAO, et al.
Published: (2017-05-01)

Combining Style Transfer in a Frame with Random Rotation Using Convolutional Neural Networks
by: Mahdi Musa Semnani, et al.
Published: (2024-10-01)

Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions
by: Kamilya Smagulova, et al.
Published: (2024-01-01)

Design of a 128‐channel transceiver hardware for medical ultrasound imaging systems
by: Jayaraj Kidav, et al.
Published: (2022-01-01)