Multi-protocol switching circuit for software defined interconnection system
In order to meet the requirements of heterogeneous protocol integration and interconnection in software-defined interconnection systems, a two-stage multi-protocol switching circuit was proposed. This circuit accommodated the forwarding needs of various heterogeneous protocols by integrating shared...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | zho |
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Editorial Department of Journal on Communications
2024-05-01
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| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/zh/article/doi/10.11959/j.issn.1000-436x.2024076/ |
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| _version_ | 1841539219709755392 |
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| author | DONG Chunlei SHEN Jianliang LI Peijie WANG Pan BO Guangming LU Kai |
| author_facet | DONG Chunlei SHEN Jianliang LI Peijie WANG Pan BO Guangming LU Kai |
| author_sort | DONG Chunlei |
| collection | DOAJ |
| description | In order to meet the requirements of heterogeneous protocol integration and interconnection in software-defined interconnection systems, a two-stage multi-protocol switching circuit was proposed. This circuit accommodated the forwarding needs of various heterogeneous protocols by integrating shared memory and Crossbar architectures. In addition, a multi-stage arbitrary scheduling scheme based on time slot was introduced to decouple time and space during the scheduling. Simulation results demonstrate that this switching circuit can dynamically adapt to changes in switching scale, port memory, and port bandwidth requirements resulting from binding mode changes. Compared to traditional combined input and output queued (CIOQ) architecture, the utilization of memory is increased by up to 87.5%, and the forwarding delay is as low as tens of nanoseconds, making it suitable for RapidIO, fibre channel (FC), Ethernet, peripheral component interconnect express (PCIe) single protocol switching as well as hybrid protocol switching combining these protocols. |
| format | Article |
| id | doaj-art-9ea223850d7846ba87fddfd396791527 |
| institution | Kabale University |
| issn | 1000-436X |
| language | zho |
| publishDate | 2024-05-01 |
| publisher | Editorial Department of Journal on Communications |
| record_format | Article |
| series | Tongxin xuebao |
| spelling | doaj-art-9ea223850d7846ba87fddfd3967915272025-01-14T07:24:21ZzhoEditorial Department of Journal on CommunicationsTongxin xuebao1000-436X2024-05-0145445362276490Multi-protocol switching circuit for software defined interconnection systemDONG ChunleiSHEN JianliangLI PeijieWANG PanBO GuangmingLU KaiIn order to meet the requirements of heterogeneous protocol integration and interconnection in software-defined interconnection systems, a two-stage multi-protocol switching circuit was proposed. This circuit accommodated the forwarding needs of various heterogeneous protocols by integrating shared memory and Crossbar architectures. In addition, a multi-stage arbitrary scheduling scheme based on time slot was introduced to decouple time and space during the scheduling. Simulation results demonstrate that this switching circuit can dynamically adapt to changes in switching scale, port memory, and port bandwidth requirements resulting from binding mode changes. Compared to traditional combined input and output queued (CIOQ) architecture, the utilization of memory is increased by up to 87.5%, and the forwarding delay is as low as tens of nanoseconds, making it suitable for RapidIO, fibre channel (FC), Ethernet, peripheral component interconnect express (PCIe) single protocol switching as well as hybrid protocol switching combining these protocols.http://www.joconline.com.cn/zh/article/doi/10.11959/j.issn.1000-436x.2024076/software defined interconnectionheterogeneous protocolswitching architecturetime division multiplexingchannel bindingmemory utilization |
| spellingShingle | DONG Chunlei SHEN Jianliang LI Peijie WANG Pan BO Guangming LU Kai Multi-protocol switching circuit for software defined interconnection system Tongxin xuebao software defined interconnection heterogeneous protocol switching architecture time division multiplexing channel binding memory utilization |
| title | Multi-protocol switching circuit for software defined interconnection system |
| title_full | Multi-protocol switching circuit for software defined interconnection system |
| title_fullStr | Multi-protocol switching circuit for software defined interconnection system |
| title_full_unstemmed | Multi-protocol switching circuit for software defined interconnection system |
| title_short | Multi-protocol switching circuit for software defined interconnection system |
| title_sort | multi protocol switching circuit for software defined interconnection system |
| topic | software defined interconnection heterogeneous protocol switching architecture time division multiplexing channel binding memory utilization |
| url | http://www.joconline.com.cn/zh/article/doi/10.11959/j.issn.1000-436x.2024076/ |
| work_keys_str_mv | AT dongchunlei multiprotocolswitchingcircuitforsoftwaredefinedinterconnectionsystem AT shenjianliang multiprotocolswitchingcircuitforsoftwaredefinedinterconnectionsystem AT lipeijie multiprotocolswitchingcircuitforsoftwaredefinedinterconnectionsystem AT wangpan multiprotocolswitchingcircuitforsoftwaredefinedinterconnectionsystem AT boguangming multiprotocolswitchingcircuitforsoftwaredefinedinterconnectionsystem AT lukai multiprotocolswitchingcircuitforsoftwaredefinedinterconnectionsystem |