Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs
The application of artificial intelligence (AI) requires advanced computation to address complex problems. However, the improvement of binary computing systems supporting these applications is approaching their limits due to atomic-level scaling. Regarding this challenging situation, ternary computi...
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IEEE
2025-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/10817560/ |
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| author | Hyundong Lee Seonghoon Kim Jongbeom Kim Jaehoon Jeong Jeonggyu Yang Taigon Song |
| author_facet | Hyundong Lee Seonghoon Kim Jongbeom Kim Jaehoon Jeong Jeonggyu Yang Taigon Song |
| author_sort | Hyundong Lee |
| collection | DOAJ |
| description | The application of artificial intelligence (AI) requires advanced computation to address complex problems. However, the improvement of binary computing systems supporting these applications is approaching their limits due to atomic-level scaling. Regarding this challenging situation, ternary computing is gaining more attention due to its better data saving/computing/moving capability. Thus, ternary logic based on various devices was proposed, but these circuits are still encountering issues of high-power consumption, low operating speed, and challenges in manufacturing compared to silicon-based circuits. Therefore, this paper presents a methodology for designing ternary logic based on Depletion-mode metal-oxide-semiconductor field-effect transistor (DEPFET) and multi-threshold voltage complementary metal-oxide–semiconductor (MTCMOS). Our silicon-based devices are easier to manufacture and support high-speed/low-power operations through our complementary ternary logic. Our balanced ternary full adder (BTFA) is <inline-formula> <tex-math notation="LaTeX">$9.70\times $ </tex-math></inline-formula> better energy efficiency than the latestcarbon nanotube field-effect transistor (CNTFET) based BTFA. We also propose the first methodology to design a ternary cell layout in multi-height standard cell design. We propose an algorithm for the best ternary cell layout and a concept of integrated layout that reduces area when required cells are close to each other. |
| format | Article |
| id | doaj-art-7cd0af169d654b728674fa00d5f0ad20 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-7cd0af169d654b728674fa00d5f0ad202025-01-03T00:01:51ZengIEEEIEEE Access2169-35362025-01-01131193120710.1109/ACCESS.2024.352334410817560Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETsHyundong Lee0https://orcid.org/0000-0002-4329-7057Seonghoon Kim1Jongbeom Kim2https://orcid.org/0009-0005-4047-976XJaehoon Jeong3https://orcid.org/0000-0001-8960-6954Jeonggyu Yang4https://orcid.org/0000-0001-9969-2307Taigon Song5https://orcid.org/0000-0001-5243-4132School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South KoreaFoundry Design Service Team, Samsung Electronics, Gyeonggi-do, South KoreaFoundry Design Service Team, Samsung Electronics, Gyeonggi-do, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South KoreaThe application of artificial intelligence (AI) requires advanced computation to address complex problems. However, the improvement of binary computing systems supporting these applications is approaching their limits due to atomic-level scaling. Regarding this challenging situation, ternary computing is gaining more attention due to its better data saving/computing/moving capability. Thus, ternary logic based on various devices was proposed, but these circuits are still encountering issues of high-power consumption, low operating speed, and challenges in manufacturing compared to silicon-based circuits. Therefore, this paper presents a methodology for designing ternary logic based on Depletion-mode metal-oxide-semiconductor field-effect transistor (DEPFET) and multi-threshold voltage complementary metal-oxide–semiconductor (MTCMOS). Our silicon-based devices are easier to manufacture and support high-speed/low-power operations through our complementary ternary logic. Our balanced ternary full adder (BTFA) is <inline-formula> <tex-math notation="LaTeX">$9.70\times $ </tex-math></inline-formula> better energy efficiency than the latestcarbon nanotube field-effect transistor (CNTFET) based BTFA. We also propose the first methodology to design a ternary cell layout in multi-height standard cell design. We propose an algorithm for the best ternary cell layout and a concept of integrated layout that reduces area when required cells are close to each other.https://ieeexplore.ieee.org/document/10817560/Multi-valued logicternary logicfull-adderdepletion-mode MOSFETlayout |
| spellingShingle | Hyundong Lee Seonghoon Kim Jongbeom Kim Jaehoon Jeong Jeonggyu Yang Taigon Song Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs IEEE Access Multi-valued logic ternary logic full-adder depletion-mode MOSFET layout |
| title | Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs |
| title_full | Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs |
| title_fullStr | Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs |
| title_full_unstemmed | Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs |
| title_short | Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs |
| title_sort | ternary toward binary circuit level implementation of ternary logic using depletion mode and conventional mosfets |
| topic | Multi-valued logic ternary logic full-adder depletion-mode MOSFET layout |
| url | https://ieeexplore.ieee.org/document/10817560/ |
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