The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter
In this study, we describe a low-noise complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC). The proposed hybrid SS-ADC provides a resolution of 11 bits in low-light and 10 bits in high-light. To this end, in the...
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MDPI AG
2024-12-01
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| Online Access: | https://www.mdpi.com/1424-8220/24/24/8131 |
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| author | Hyun Seon Choo Da-Hyeon Youn Hyunggyu Choi Gi Yeol Kim Soo Youn Kim |
| author_facet | Hyun Seon Choo Da-Hyeon Youn Hyunggyu Choi Gi Yeol Kim Soo Youn Kim |
| author_sort | Hyun Seon Choo |
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| description | In this study, we describe a low-noise complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC). The proposed hybrid SS-ADC provides a resolution of 11 bits in low-light and 10 bits in high-light. To this end, in the low-light section, the digital-correlated double sampling method using a double data rate structure was used to obtain a noise performance similar to that of the 11-bit SS-ADC under low-light conditions, while maintaining linear in-out characteristics. The CIS with the proposed 10/11-bit hybrid SS-ADC was fabricated using a 110 nm 1-poly 4-metal CIS process. The measurement results showed that dark random noise was reduced by 8% in low light when using the proposed hybrid SS-ADC, compared with the existing 10-bit ADC. Additionally, in the case of high brightness, when using a 10-bit resolution, the dynamic power consumption decreased by approximately 31%, compared to the 11-bit ADC. The total power consumption is 3.9 mW at 15 fps when the analog, pixel, and digital supply voltages are 3.3 V, 3.3 V, and 1.5 V, respectively. |
| format | Article |
| id | doaj-art-7b24b839a0334bcaa44e6c9bb7ea2187 |
| institution | Kabale University |
| issn | 1424-8220 |
| language | English |
| publishDate | 2024-12-01 |
| publisher | MDPI AG |
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| series | Sensors |
| spelling | doaj-art-7b24b839a0334bcaa44e6c9bb7ea21872024-12-27T14:53:05ZengMDPI AGSensors1424-82202024-12-012424813110.3390/s24248131The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital ConverterHyun Seon Choo0Da-Hyeon Youn1Hyunggyu Choi2Gi Yeol Kim3Soo Youn Kim4Department of System Semiconductor, Dongguk University, Seoul 04620, Republic of KoreaDepartment of System Semiconductor, Dongguk University, Seoul 04620, Republic of KoreaDepartment of System Semiconductor, Dongguk University, Seoul 04620, Republic of KoreaDepartment of System Semiconductor, Dongguk University, Seoul 04620, Republic of KoreaDepartment of System Semiconductor, Dongguk University, Seoul 04620, Republic of KoreaIn this study, we describe a low-noise complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC). The proposed hybrid SS-ADC provides a resolution of 11 bits in low-light and 10 bits in high-light. To this end, in the low-light section, the digital-correlated double sampling method using a double data rate structure was used to obtain a noise performance similar to that of the 11-bit SS-ADC under low-light conditions, while maintaining linear in-out characteristics. The CIS with the proposed 10/11-bit hybrid SS-ADC was fabricated using a 110 nm 1-poly 4-metal CIS process. The measurement results showed that dark random noise was reduced by 8% in low light when using the proposed hybrid SS-ADC, compared with the existing 10-bit ADC. Additionally, in the case of high brightness, when using a 10-bit resolution, the dynamic power consumption decreased by approximately 31%, compared to the 11-bit ADC. The total power consumption is 3.9 mW at 15 fps when the analog, pixel, and digital supply voltages are 3.3 V, 3.3 V, and 1.5 V, respectively.https://www.mdpi.com/1424-8220/24/24/8131CMOS image sensorcorrelated double samplingdouble data ratehybrid single-slope ADClow noise |
| spellingShingle | Hyun Seon Choo Da-Hyeon Youn Hyunggyu Choi Gi Yeol Kim Soo Youn Kim The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter Sensors CMOS image sensor correlated double sampling double data rate hybrid single-slope ADC low noise |
| title | The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter |
| title_full | The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter |
| title_fullStr | The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter |
| title_full_unstemmed | The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter |
| title_short | The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter |
| title_sort | design of a low noise cmos image sensor using a hybrid single slope analog to digital converter |
| topic | CMOS image sensor correlated double sampling double data rate hybrid single-slope ADC low noise |
| url | https://www.mdpi.com/1424-8220/24/24/8131 |
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