Scalable High-Throughput and Low-Latency DVB-S2(x) LDPC Decoders on SIMD Devices
Low-density parity-check (LDPC) codes are error correction codes (ECC) with near Shannon correction performances limit boosting the reliability of digital communication systems using them. Their efficiency goes hand in hand with their high computational complexity resulting in a computational bottle...
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Communications Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10747211/ |
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| Summary: | Low-density parity-check (LDPC) codes are error correction codes (ECC) with near Shannon correction performances limit boosting the reliability of digital communication systems using them. Their efficiency goes hand in hand with their high computational complexity resulting in a computational bottleneck in physical layer processing. Solutions based on multicore and many-core architectures have been proposed to support the development of software-defined radio and virtualized radio access networks (vRANs). Many studies focused on the efficient parallelization of LDPC decoding algorithms. In this study, we propose an efficient SIMD parallelization strategy for DVB-S2(x) LDPC codes. It achieves throughputs from 7 Gbps to 12 Gbps on an INTEL Xeon Gold target when 10 layered decoding iterations are executed. Simultaneously, the latencies are lower than <inline-formula> <tex-math notation="LaTeX">$400~\mu $ </tex-math></inline-formula>s. These performances are equivalent to FPGA-based solutions and overclass CPU and GPU related works by factors up to <inline-formula> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula>. |
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| ISSN: | 2644-125X |