Optimization of Multi-Fins FinFET Implemented on SOI Wafer Based on SiGe and Gaussian Process Regression
Despite advancements in mitigating the short channel effect using high-k materials, multi-gate structures, and silicon-germanium (SiGe) alloys in three-dimensional FinFETs, performance trade-offs remain. This study introduces a novel machine learning framework utilizing a Gaussian process regression...
Saved in:
| Main Authors: | Christofer N. Yalung, Wittawat Yamwong, Doldet Tantraviwat |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10741230/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance
by: Priyanka Agrwal, et al.
Published: (2025-02-01) -
Process-Dependent Evolution of Channel Stress and Stress-Induced Mobility Gain in FinFET, Normal GAAFET, and Si/SiGe Hybrid Channel GAAFET
by: Chiang Zhu, et al.
Published: (2025-01-01) -
Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
by: Shivendra Singh Parihar, et al.
Published: (2025-01-01) -
Memristive Ferroelectric FET for 1T-1R Nonvolatile Memory With Non-Destructive Readout
by: Roopesh Singh, et al.
Published: (2025-01-01) -
A Unified Semiconductor-Device-Physics-Based Ballistic Model for the Threshold Voltage of Modern Multiple-Gate Metal-Oxide-Semiconductor Field-Effect-Transistors
by: Te-Kuang Chiang
Published: (2024-12-01)