Introducing Primality Testing Algorithm with an Implementation on 64 bits RSA Encryption Using Verilog

Introducing Primality Testing Algorithm with an Implementation on 64 bits RSA Encryption Using Verilog

A new structure to develop 64-bit RSA encryption engine on FPGA is being presented in this paper that can be used as a standard device in the secured communication system. The RSA algorithm has three parts i.e. key generation, encryption and decryption. This procedure also requires random generatio...

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Bibliographic Details
Main Authors: Rehan Shams, Fozia Hanif Khan, Umair Jillani, M. Umair
Format: Article
Language:English
Published: Sir Syed University of Engineering and Technology, Karachi. 2018-12-01
Series:Sir Syed University Research Journal of Engineering and Technology
Subjects:
RSA, Verilog, Cryptosystem, Primality Testing, Decryption, Encryption, Implementation, Key Generation, Modular Exponentiation
Online Access:http://www.sirsyeduniversity.edu.pk/ssurj/rj/index.php/ssurj/article/view/68
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