Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS
The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design...
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2025-01-01
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| author | Roberto Rubino Francesco Musolino Pedro Toledo Yong Chen Anna Richelli Paolo S. Crovetti |
| author_facet | Roberto Rubino Francesco Musolino Pedro Toledo Yong Chen Anna Richelli Paolo S. Crovetti |
| author_sort | Roberto Rubino |
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| description | The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design is a single-ended ReDAC (SE-ReDAC) and operates at 880kS/s with a 10-bit resolution, while the second is based on a differential ReDAC (Diff-ReDAC) architecture and operates at 100kS/s with a 13-bit resolution. The SE-ReDAC testchip in 180nm occupies just 5,030<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m2 and operates with a supply voltage ranging from 0.6V to 1V. Experimental results at 0.65V reveal a 72.18dB-SFDR, a 65.59dB-THD and a 56.09dB SINAD, resulting in 9.02ENOB, with a power dissipation of just <inline-formula> <tex-math notation="LaTeX">$3.3\mu $ </tex-math></inline-formula> W, achieving a competitive energy-efficiency (area-normalized energy efficiency) figure of merit FOM (<inline-formula> <tex-math notation="LaTeX">$\mathrm {FOM_{A}}$ </tex-math></inline-formula>) of 166dB (175dB). On the other hand, the 180-nm Diff-ReDAC testchip occupies 7,800<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m2 and operates in a supply voltage range from 0.45V to 1V, while achieving a 77.81dB-SFDR, a 77.52dB-THD and a 65.82dB-SINAD (10.64ENOB) at 0.6V supply with a power consumption of just 880nW, leading to a very competitive FOM (FOMA) of 172dB (178dB). |
| format | Article |
| id | doaj-art-1eeb864228e44ae797bad68c50186cf5 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
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| series | IEEE Access |
| spelling | doaj-art-1eeb864228e44ae797bad68c50186cf52025-01-15T00:02:22ZengIEEEIEEE Access2169-35362025-01-01136594660510.1109/ACCESS.2025.352620910829600Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOSRoberto Rubino0Francesco Musolino1https://orcid.org/0000-0001-9960-4653Pedro Toledo2https://orcid.org/0000-0002-5084-491XYong Chen3Anna Richelli4https://orcid.org/0000-0003-4269-1228Paolo S. Crovetti5https://orcid.org/0000-0002-2484-1686Analog Devices, Bari, ItalyDepartment of Electronics and Telecommunications (DET), Politecnico di Torino, Turin, ItalySynopsys, Lisbon, PortugalDepartment of Electronic Engineering, Tsinghua University, Beijing, ChinaDepartment of Information Engineering, University of Brescia, Brescia, ItalyDepartment of Electronics and Telecommunications (DET), Politecnico di Torino, Turin, ItalyThe design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design is a single-ended ReDAC (SE-ReDAC) and operates at 880kS/s with a 10-bit resolution, while the second is based on a differential ReDAC (Diff-ReDAC) architecture and operates at 100kS/s with a 13-bit resolution. The SE-ReDAC testchip in 180nm occupies just 5,030<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m2 and operates with a supply voltage ranging from 0.6V to 1V. Experimental results at 0.65V reveal a 72.18dB-SFDR, a 65.59dB-THD and a 56.09dB SINAD, resulting in 9.02ENOB, with a power dissipation of just <inline-formula> <tex-math notation="LaTeX">$3.3\mu $ </tex-math></inline-formula> W, achieving a competitive energy-efficiency (area-normalized energy efficiency) figure of merit FOM (<inline-formula> <tex-math notation="LaTeX">$\mathrm {FOM_{A}}$ </tex-math></inline-formula>) of 166dB (175dB). On the other hand, the 180-nm Diff-ReDAC testchip occupies 7,800<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m2 and operates in a supply voltage range from 0.45V to 1V, while achieving a 77.81dB-SFDR, a 77.52dB-THD and a 65.82dB-SINAD (10.64ENOB) at 0.6V supply with a power consumption of just 880nW, leading to a very competitive FOM (FOMA) of 172dB (178dB).https://ieeexplore.ieee.org/document/10829600/D/A converter (DAC)relaxation D/A converter (ReDAC)ultra-low areadigital-basedultra-low powerultra-low voltage |
| spellingShingle | Roberto Rubino Francesco Musolino Pedro Toledo Yong Chen Anna Richelli Paolo S. Crovetti Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS IEEE Access D/A converter (DAC) relaxation D/A converter (ReDAC) ultra-low area digital-based ultra-low power ultra-low voltage |
| title | Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS |
| title_full | Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS |
| title_fullStr | Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS |
| title_full_unstemmed | Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS |
| title_short | Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS |
| title_sort | relaxation digital to analog converters featuring self calibration and parasitics induced error suppression in 180 nm cmos |
| topic | D/A converter (DAC) relaxation D/A converter (ReDAC) ultra-low area digital-based ultra-low power ultra-low voltage |
| url | https://ieeexplore.ieee.org/document/10829600/ |
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