9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage
Abstract With the development of processes and reduction of transistor size, transistor sensitivity to voltage changes has increased. Traditional SRAM bit cells struggle to function properly at low voltages, and the lengthy write time necessitated by the write conflict problem will inevitably result...
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| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2024-09-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.70039 |
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| _version_ | 1846173399316955136 |
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| author | Chenjie Jiang Junqi Wen Siyu Meng Kepu Fu Changquan Xia Haitao Chen Qinyu Qian Liwen Cheng |
| author_facet | Chenjie Jiang Junqi Wen Siyu Meng Kepu Fu Changquan Xia Haitao Chen Qinyu Qian Liwen Cheng |
| author_sort | Chenjie Jiang |
| collection | DOAJ |
| description | Abstract With the development of processes and reduction of transistor size, transistor sensitivity to voltage changes has increased. Traditional SRAM bit cells struggle to function properly at low voltages, and the lengthy write time necessitated by the write conflict problem will inevitably result in write failure. As ultra‐low‐voltage SRAM has emerged as a significant direction of research for SRAM, this paper proposes an ultra‐low‐voltage 9T SRAM bit cell that is conflict‐free. By circumventing write conflicts and enabling rapid writing, the bit cell demonstrates its superiority, particularly at ultra‐low voltages, by eliminating the requirement for peripheral write‐assist circuitry to accomplish chip writing. To assess the performance of the conflict‐free 9T bit cell, simulation experiments are conducted utilizing the 28 nm process model. Simulation results indicate that the 9T bit cell proposed in this paper requires only 66% of the writing time of the traditional 6T cell. This enables the cell to accomplish fast writing and more stable writing performance. |
| format | Article |
| id | doaj-art-1cf1f81d74ea4438acb790b7157a5af1 |
| institution | Kabale University |
| issn | 0013-5194 1350-911X |
| language | English |
| publishDate | 2024-09-01 |
| publisher | Wiley |
| record_format | Article |
| series | Electronics Letters |
| spelling | doaj-art-1cf1f81d74ea4438acb790b7157a5af12024-11-08T14:35:50ZengWileyElectronics Letters0013-51941350-911X2024-09-016017n/an/a10.1049/ell2.700399T fast‐write SRAM bit cell with no conflicts for ultra‐low voltageChenjie Jiang0Junqi Wen1Siyu Meng2Kepu Fu3Changquan Xia4Haitao Chen5Qinyu Qian6Liwen Cheng7College of Physical Science and Technology & Microelectronics Industry Research Institute Yangzhou University Yangzhou ChinaCollege of Physical Science and Technology & Microelectronics Industry Research Institute Yangzhou University Yangzhou ChinaCollege of Physical Science and Technology & Microelectronics Industry Research Institute Yangzhou University Yangzhou ChinaCollege of Physical Science and Technology & Microelectronics Industry Research Institute Yangzhou University Yangzhou ChinaCollege of Physical Science and Technology & Microelectronics Industry Research Institute Yangzhou University Yangzhou ChinaCollege of Physical Science and Technology & Microelectronics Industry Research Institute Yangzhou University Yangzhou ChinaCollege of Physical Science and Technology & Microelectronics Industry Research Institute Yangzhou University Yangzhou ChinaCollege of Physical Science and Technology & Microelectronics Industry Research Institute Yangzhou University Yangzhou ChinaAbstract With the development of processes and reduction of transistor size, transistor sensitivity to voltage changes has increased. Traditional SRAM bit cells struggle to function properly at low voltages, and the lengthy write time necessitated by the write conflict problem will inevitably result in write failure. As ultra‐low‐voltage SRAM has emerged as a significant direction of research for SRAM, this paper proposes an ultra‐low‐voltage 9T SRAM bit cell that is conflict‐free. By circumventing write conflicts and enabling rapid writing, the bit cell demonstrates its superiority, particularly at ultra‐low voltages, by eliminating the requirement for peripheral write‐assist circuitry to accomplish chip writing. To assess the performance of the conflict‐free 9T bit cell, simulation experiments are conducted utilizing the 28 nm process model. Simulation results indicate that the 9T bit cell proposed in this paper requires only 66% of the writing time of the traditional 6T cell. This enables the cell to accomplish fast writing and more stable writing performance.https://doi.org/10.1049/ell2.70039circuit simulationCMOS memory circuits |
| spellingShingle | Chenjie Jiang Junqi Wen Siyu Meng Kepu Fu Changquan Xia Haitao Chen Qinyu Qian Liwen Cheng 9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage Electronics Letters circuit simulation CMOS memory circuits |
| title | 9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage |
| title_full | 9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage |
| title_fullStr | 9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage |
| title_full_unstemmed | 9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage |
| title_short | 9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage |
| title_sort | 9t fast write sram bit cell with no conflicts for ultra low voltage |
| topic | circuit simulation CMOS memory circuits |
| url | https://doi.org/10.1049/ell2.70039 |
| work_keys_str_mv | AT chenjiejiang 9tfastwritesrambitcellwithnoconflictsforultralowvoltage AT junqiwen 9tfastwritesrambitcellwithnoconflictsforultralowvoltage AT siyumeng 9tfastwritesrambitcellwithnoconflictsforultralowvoltage AT kepufu 9tfastwritesrambitcellwithnoconflictsforultralowvoltage AT changquanxia 9tfastwritesrambitcellwithnoconflictsforultralowvoltage AT haitaochen 9tfastwritesrambitcellwithnoconflictsforultralowvoltage AT qinyuqian 9tfastwritesrambitcellwithnoconflictsforultralowvoltage AT liwencheng 9tfastwritesrambitcellwithnoconflictsforultralowvoltage |