Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State

Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State

To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time. In such systems, when installing different caches in different processors in shared memory architecture,...

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Bibliographic Details
Main Author: Baghdad Science Journal
Format: Article
Language:English
Published: University of Baghdad, College of Science for Women 2017-03-01
Series:مجلة بغداد للعلوم
Subjects:
Cache Coherence Problem, Snooping Protocol, Directory-Based Cache Protocols, MESI, Cache Simulator, Dev. C , Multiprocessor, Shared Memory
Online Access:http://bsj.uobaghdad.edu.iq/index.php/BSJ/article/view/2355
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http://bsj.uobaghdad.edu.iq/index.php/BSJ/article/view/2355

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