Reducing Avalanche Build-Up Time by Integrating a Single-Photon Avalanche Diode with a BiCMOS Gating Circuit
It is shown that the integration of a single-photon avalanche diode (SPAD) together with a BiCMOS gating circuit on one chip reduces the parasitic capacitance a lot and therefore reduces the avalanche build-up time. The capacitance of two bondpads, which are necessary for the connection of an SPAD c...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2024-11-01
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| Series: | Sensors |
| Subjects: | |
| Online Access: | https://www.mdpi.com/1424-8220/24/23/7598 |
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