Investigation of the Timing Parameters of The Arbiter-Based Physically Unclonable Function Using a Ring Oscillator by A. Yu. Shamyna, A. A. Ivaniuk

“…The possibility of using a ring oscillator circuit for measuring the propagation delays of signals through symmetrical APUF paths of various lengths implemented on an FPGA is considered. The creation of the experimental setup and the course of the experiments are described. …”
Get full text

An Improved Toeplitz Measurement Matrix for Compressive Sensing by Xu Su, Yin Hongpeng, Chai Yi, Xiong Yushu, Tan Xue

“…However, the random measurement matrix is hard to implement by hardware. So the randomness of the measurement matrix leads to the poor performance of signal reconstruction. …”
Get full text

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems by E. Romero-Aguirre, R. Parra-Michel, Roberto Carrasco-Alvarez, A. G. Orozco-Lugo

“…The synthesis results showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115 MHz operating frequencies, respectively. …”
Get full text

Design of Wireless Automatic Synchronization for the Low-Frequency Coded Ground Penetrating Radar by Zhenghuan Xia, Qunying Zhang, Shengbo Ye, Zhiwu Xu, Jie Chen, Guangyou Fang, Hejun Yin

“…All the processes are performed in a single FPGA. The performance of the proposed synchronization method is validated with experiment.…”
Get full text

Self-Adaptive On-Chip System Based on Cross-Layer Adaptation Approach by Kais Loukil, Nader Ben Amor, Mohamed Abid, Jean Philippe Diguet

“…The proposed approach has been applied to a 3D graphics application and successfully implemented on an Altera FPGA.…”
Get full text

A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos by Alba Sandyra Bezerra Lopes, Ivan Saraiva Silva, Luciano Volcan Agostini

“…A case study for the proposed hierarchy, using 32×32 search window and 8×8 block size, was implemented and prototyped on a Virtex 4 FPGA. The results show that it is possible to reach 38 frames per second when processing full HD frames (1920×1080 pixels) using nearly 299 Mbytes per second of external memory bandwidth.…”
Get full text

Design of a Hierarchical Control Architecture for Fully-Driven Multi-Fingered Dexterous Hand by Yinan Jin, Hujiang Wang, Han Ge, Guanjun Bao

“…The software implements a fuzzy PID algorithm that dynamically adjusts PID parameters based on both the error and the error rate, thereby effectively managing the nonlinear behaviors of the hand. …”
Get full text

Advanced vehicle-to-grid control: enhancing energy exchange and power quality with grey wolf optimized bidirectional converters in EV charging infrastructure by Nagarajan Munusamy, Indragandhi Vairavasundaram

“…Offline-optimized benefits are confirmed robust by implementing them on a Xilinx Spartan-6 FPGA hardware prototype. …”
Get full text

L-Sort: On-Chip Spike Sorting With Efficient Median-of-Median Detection and Localization-Based Clustering by Yuntao Han, Yihan Pan, Xiongfei Jiang, Cristian Sestito, Shady Agwa, Themis Prodromakis, Shiwei Wang

“…Evaluation using Neuropixels datasets demonstrates that L-Sort achieves competitive sorting accuracy with reduced hardware resource consumption. Implementations on FPGA and ASIC (180 nm technology) demonstrate significant improvements in area and power efficiency compared to state-of-the-art designs while maintaining comparable accuracy. …”
Get full text