LR-FHSS Transceiver for Direct-to-Satellite IoT Communications: Design, Implementation, and Verification by Sooyeob Jung, Seongah Jeong, Jinkyu Kang, Gyeongrae Im, Sangjae Lee, Mi-Kyung Oh, Joon Gyu Ryu, Joonhyuk Kang

“…Lastly, we present proof-of-concept implementation and testbeds using an application-specific integrated circuit (ASIC) chipset and a field-programmable gate array (FPGA) that verify the performance of the proposed LR-FHSS transceiver design of DtS-IoT communication systems. …”
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Design and implementation of a low-power position monitoring and control system for on-orbit focusing. by Leijie Jiang, Keyu Guo, Xin Liu, Zhenzhong Zhang

“…The performances of the designed system are implemented on a field programmable gate array (FPGA) circuit board. …”
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Synthesis of parallel adders from if-decision diagrams by A. A. Prihozhy

“…For decades, extensive research has been done devoted to designing higher speed and less complex adder architectures, and to developing advanced adder implementation technologies. Decision diagrams are a promising approach to the efficient many-bit adder design. …”
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BGIR: A Low-Illumination Remote Sensing Image Restoration Algorithm with ZYNQ-Based Implementation by Zhihao Guo, Liangliang Zheng, Wei Xu

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EVALUATING TIME AND VOLUME CHARACTERISTICS OF HARDWARE IMPLEMENTATION OF CRYPTOGRAPHIC ALGORITHMS IN STANDARD STB 34.101.31–2011 by A. S. Poljakov, V. E. Samsonov

“…Processing time and hardware requirements of hardware implementation of 8 algorithms of national standard of the Republic Belarus based on FPGA microchips are provided. …”
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Design and Implementation of Power Management System in Multi-String Solar-Interfaced DC Microgrid With Energy Storage System by V. Srimathi, D. Vijayakumar

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Hardware-in-loop implementation of an adaptive MPPT controlled PV-assisted EV charging system with vehicle-to-grid integration by Surabhi Singh, Hari Om Bansal

“…The overall system is validated in a hardware-in-loop real-time environment through FPGA-based OPAL-RT.…”
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A Dual Polyphase Decomposition Overlapped Polyphase Filter Bank and Its Implementation in a Field-programmable Gate Array by Shaocong Guo, Qiao Meng, Hailong Zhang, Yazhou Zhang, Chenye Zhou, Gaojing Li, Jie Wu, Jianxun Shao

“…It significantly simplifies the FPGA implementation of the OPFB with wideband output subbands.…”
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SHM System for Composite Material Based on Lamb Waves and Using Machine Learning on Hardware by Gracieth Cavalcanti Batista, Carl-Mikael Zetterling, Johnny Öberg, Osamu Saotome

“…For this reason, the present paper introduces an FPGA-based intelligent SHM system that processes Lamb wave signals using piezoelectric sensors to detect, classify, and locate damage in composite structures. …”
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Investigation of the physically unclonable function of a configurable ring oscillator by A. A. Ivaniuk

“…Objectives. Design and implementation features of a Physically Unclonable Function (PUF) based on a Configurable Ring Oscillator (CRO) on FPGA platforms are examined. …”
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Highly-Efficient Hardware Architecture for ML-KEM PQC Standard by Haesung Jung, Quang Dang Truong, Hanho Lee

“…The proposed architecture is validated through implementation on an Artix-7 FPGA and Synopsys 14nm ASIC technology. …”
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Design of a Heterogeneous-Based Network Intrusion Detection System and Compiler by Zhigui Lin, Xiaofeng Zhang, Qi Liu, Jun Cui

“…We construct an FPGA + CPU heterogeneous detection system featuring a five-tuple segmented matching architecture, which integrates hash bitmap and shift-or algorithms to achieve fast-pattern matching. …”
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Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography by Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu

“…The method is experimentally validated using observations of the electromagnetic near field distribution over a Xilinx Virtex 5 FPGA. The matching between areas of interest and the application layout in the FPGA floorplan is confirmed by correlation analysis.…”
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Error Detection and Correction On-Board Nanosatellites Using Hamming Codes by Caleb Hillier, Vipin Balyan

“…All developed Hamming codes are suited for FPGA implementation, for which they are tested thoroughly using simulation software and optimized.…”
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Cellular Automata-Based Parallel Random Number Generators Using FPGAs by David H. K. Hoe, Jonathan M. Comer, Juan C. Cerda, Chris D. Martinez, Mukul V. Shirvaikar

“…This is advantageous for FPGA designs due to the compactness of the LFSR implementations. …”
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Neuromorphic Configurable Architecture for Robust Motion Estimation by Guillermo Botella, Manuel Rodríguez, Antonio García, Eduardo Ros

“…This novel customizable architecture of a neuromorphic robust optical flow can be constructed with FPGA or ASIC device using properties of the cortical motion pathway, constituting a useful framework for building future complex bioinspired systems running in real time with high computational complexity. …”
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INCREASE OF EFFICIENCY OF SUPPRESSION OF THE ACTIVE NOISE JAMMING IN RADAR INTERCEPTION OF AIR TARGETS IN THE REVIEW MODE by V. E. Markevich

“…Advantage of algorithm of compensating of the active noises jamming, using the recurrence estimation of a inverse covariance matrix of jamming is shown.The algorithm of functioning on the basis of SRM allows to lower essentially requirements to specialized VLSI (FPGA) at implementation is hardware – program complexes for preprocessing of the radar, radio communication and radio – navigation information in the conditions of influence of the active noises jamming in the presence of effects of multipath propagation of signals, in the presence of delay of signals on an antenna system aperture, and also at unremovable technological dispersion amplitude and phase characteristics of the microwave of channels of handling.…”
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Physically unclonable functions with controlled propagation delay by V. N. Yarmolik, A. A. Ivaniuk, N. N. Shynkevich

“…Methods  of  synthesis  and  analysis  of  digital  devices  were  used,  including  those  based  on programmable logic integrated circuits (FPGA), the basics of Boolean algebra and circuitry.R e s u l t s. …”
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High-Level Synthesis: Productivity, Performance, and Software Constraints by Yun Liang, Kyle Rupnow, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen

“…However, design effort for FPGA implementations remains high—often an order of magnitude larger than design effort using high-level languages. …”
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A Study of the Optimal Logic Combinations of RO-Based PUFs on FPGAs to Maximize Identifiability by Raúl Aparicio-Téllez, Miguel Garcia-Bosque, Guillermo Díez-Señorans, Francisco Aznar, Santiago Celma

“…Thus, the architecture of GenGAROs is analyzed to implement a GenGARO-PUF on an Artix-FPGA. With this purpose, an exhaustive study of logical operation combinations that optimize PUF performance in terms of identifiability has been conducted. …”
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