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Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters
Published 2022-01-01Subjects: “…Field programmable gate arrays…”
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22
Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture
Published 2021-11-01Subjects: “…field programmable gate arrays…”
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23
An efficient loop tiling framework for convolutional neural network inference accelerators
Published 2022-01-01Subjects: “…field programmable gate arrays…”
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24
Design, Implementation, and Analysis of High-Speed Single-Stage N-Sorters and N-Filters
Published 2021-01-01Subjects: “…Field programmable gate arrays…”
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25
Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication
Published 2021-08-01Subjects: “…field programmable gate arrays…”
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26
FPGA‐based implementation of floating point processing element for the design of efficient FIR filters
Published 2021-07-01Subjects: Get full text
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27
Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme
Published 2021-11-01Subjects: Get full text
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28
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
Published 2021-09-01Subjects: Get full text
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29
FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing
Published 2021-11-01Subjects: Get full text
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30
Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
Published 2021-08-01Subjects: Get full text
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31
Design of a 128‐channel transceiver hardware for medical ultrasound imaging systems
Published 2022-01-01Subjects: Get full text
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32
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Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies
Published 2025-01-01Subjects: Get full text
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