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Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell
Published 2021-10-01“…Abstract A memristor‐transistor hybrid ternary content addressable memory (MTCAM) with a memristor‐based ternary memory cell is proposed. …”
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OpenFlow table lookup scheme integrating multiple-cell Hash table with TCAM
Published 2016-10-01Subjects: Get full text
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A simple model for Behavioral Time Scale Synaptic Plasticity (BTSP) provides content addressable memory with binary synapses and one-shot learning
Published 2025-01-01“…They also provide a promising approach for implementing content-addressable memory with on-chip learning capability in highly energy-efficient crossbar arrays of memristors.…”
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SpaceCAM: A 16 nm FinFET Low-Power Soft-Error Tolerant TCAM Design for Space Communication Applications
Published 2025-01-01Subjects: Get full text
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Monolithic 3-D-Based Nonvolatile Associative Processor for High-Performance Energy-Efficient Computations
Published 2024-01-01Subjects: Get full text
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MEFET-Based CAM/TCAM for Memory-Augmented Neural Networks
Published 2024-01-01Subjects: “…Content-addressable memory (CAM)…”
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ADAFT:an storage architecture of large-scale SDN flow tables based on adaptive deep aggregations
Published 2024-05-01“…To solve the problem of resource shortage of ternary content addressable memory (TCAM) in the data plane of software defined network (SDN), a deep flow table aggregation method was proposed based on content entry trees, and a storage architecture of large-scale SDN flow tables named ADAFT was established. …”
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Exposing End-to-End Delay in Software-Defined Networking
Published 2019-01-01“…Furthermore, we study the impact on packet delay caused by ternary content addressable memory (TCAM) update. We measure parameters in the delay model and find that if SDN is deployed in all segments of WAN, the delay of packet traversal will be increased up to 27.95 times in the worst case in our experimental settings, compared with the delay in conventional network. …”
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Low-power edge detection based on ferroelectric field-effect transistor
Published 2025-01-01“…Different from the conventional edge detectors requiring sophisticated hardware for the complex operation such as convolution and gradient, the proposed edge detector is analogue-to-digital converter free and loaded into a multi-bit content addressable memory, which only needs one 4 × 4 ferroelectric field-effect transistor NAND array. …”
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NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution
Published 2012-01-01“…However, conventional non-blocking cache designs are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This work proposes NCOR, an FPGA-friendly non-blocking cache that exploits the key properties of Runahead execution. …”
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