E-MAC: Enhanced In-SRAM MAC Accuracy via Digital-to-Time Modulation by Saeed Seyedfaraji, Salar Shakibhamedan, Amire Seyedfaraji, Baset Mesgari, Nima Taherinejad, Axel Jantsch, Semeen Rehman

Subjects: “…6T-static random access memory (SRAM)…”
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Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering by Xuexiang Zhang, Qingkun Li, Lei Cao, Qingzhu Zhang, Renjie Jiang, Peng Wang, Jiaxin Yao, Huaxiang Yin

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Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures by Shivendra Singh Parihar, Girish Pahwa, Baker Mohammad, Yogesh Singh Chauhan, Hussam Amrouch

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Capacitance and Conductance Compensation Methods for Efficient Computing‐In‐Memory Designs by Yubiao Luo, Fei Qiao, Zhong Sun

“…Here, the capacitance and conductance compensation methods are reviewed that have been used for CIM designs based on static random‐access memory (SRAM) in combination with capacitors and nonvolatile resistive memory, respectively, and uncover the underlying principles and their application to CIM. …”
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Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling by S. Narendran, J. Selvakumar

“…We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM). We attained the low power by connecting a shared/common bit line and using a 1-bit memory cell. …”
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CNN Accelerator Performance Dependence on Loop Tiling and the Optimum Resource-Constrained Loop Tiling by Chester Sungchung Park, Sungkyung Park

“…The analysis provides a useful insight into how to determine the tile sizes to achieve the required performance while avoiding an unnecessary static random access memory (SRAM) size increase. The paper also deals with the optimum resource-constrained loop tiling for CNN accelerators. …”
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Soft Error-Tolerant and Highly Stable Low-Power SRAM for Satellite Applications by Jong-Yeob Oh, Sung-Hun Jo

“…As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. …”
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Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design by Mathan Natarajamoorthy, Jayashri Subbiah, Nurul Ezaila Alias, Michael Loong Peng Tan

“…GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. …”
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A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor by Vipin Kumar Sharma, Abhishek Kumar

“…Abstract The 8T static random-access memory (SRAM) cell using carbon nanotube technology, positive feedback, and dynamic supply voltage scaling are presented in this work. …”
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A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power by Sanket M. Mantrashetti, Arunkumar P Chavan, Prakash Pawar, H. V. Ravish Aradhya, Omkar S. Powar

“…This paper introduces a novel algorithm for optimizing transistor sizing in static random-access memory (SRAM) to enhance speed, improve Static Noise Margin (SNM), and reduce leakage power consumption. …”
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System-Technology Co-Optimization for Dense Edge Architectures Using 3-D Integration and Nonvolatile Memory by Leandro M. Giacomini Rocha, Mohamed Naeim, Guilherme Paim, Moritz Brunion, Priya Venugopal, Dragomir Milojevic, James Myers, Mustafa Badaroglu, Marian Verhelst, Julien Ryckaert, Dwaipayan Biswas

“…We observe that the 3-D system integration of static random-access memory (SRAM)-based design leads to 9% power savings with 53% footprint reduction at iso-frequency with respect to 2-D implementation for the same memory capacity. …”
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