Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip
Long left ignored by the digital computing industry since its heyday in 1940’s, analog computing is today making a comeback as Moore’s Law slows down. Analog CMOS has power efficiency advantages over digital CMOS for low-precision applications in edge computing, scientific comp...
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2025-01-01
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| author | Hasantha Malavipathirana Soumyajit Mandal Nilan Udayanga Yingying Wang S. I. Hariharan Arjuna Madanayake |
| author_facet | Hasantha Malavipathirana Soumyajit Mandal Nilan Udayanga Yingying Wang S. I. Hariharan Arjuna Madanayake |
| author_sort | Hasantha Malavipathirana |
| collection | DOAJ |
| description | Long left ignored by the digital computing industry since its heyday in 1940’s, analog computing is today making a comeback as Moore’s Law slows down. Analog CMOS has power efficiency advantages over digital CMOS for low-precision applications in edge computing, scientific computing, and artificial intelligence/machine learning (AI/ML) verticals. Driven by observed non-trivial improvements in performance over digital processors while solving linear partial differential equations (PDEs), this paper presents experimental results and analysis from a single-chip CMOS analog computer for solving nonlinear PDEs. The chip integrates a 15-point fully-parallel spatially-discrete time-continuous (SDTC) finite difference time-domain (FDTD) solver for acoustic shock wave equations with radiation boundary conditions. The design was realized in TSMC 180 nm CMOS technology. It has an active area of 7.38 mm<inline-formula> <tex-math notation="LaTeX">$\times 4.64$ </tex-math></inline-formula> mm and consumes 936 mW while delivering an equivalent FDTD temporal update rate of 80 MHz and an analog bandwidth of 2 MHz. The paper discusses the challenges and associated design trade-offs in realizing such high-performance CMOS analog computers, including sensitivity to process, voltage, and temperature (PVT) variations, sensitivity to bias and voltage regulation, errors associated with noise, difficulties with calibration; it also outlines possible approaches for mitigating these challenges. |
| format | Article |
| id | doaj-art-f71964c5a7444b4b895fe7abda2b6fb1 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
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| spelling | doaj-art-f71964c5a7444b4b895fe7abda2b6fb12025-01-10T00:02:49ZengIEEEIEEE Access2169-35362025-01-01132862287510.1109/ACCESS.2024.352450010818682Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS ChipHasantha Malavipathirana0https://orcid.org/0000-0002-3607-8198Soumyajit Mandal1https://orcid.org/0000-0001-9070-2337Nilan Udayanga2Yingying Wang3S. I. Hariharan4https://orcid.org/0000-0001-6541-8860Arjuna Madanayake5https://orcid.org/0000-0003-3478-6702Department of Electrical and Computer Engineering, Florida International University, Miami, FL, USAInstrumentation Division, Brookhaven National Laboratory, Upton, NY, USADepartment of Electrical and Computer Engineering, Florida International University, Miami, FL, USAOcius Technologies, Akron, OH, USAOcius Technologies, Akron, OH, USADepartment of Electrical and Computer Engineering, Florida International University, Miami, FL, USALong left ignored by the digital computing industry since its heyday in 1940’s, analog computing is today making a comeback as Moore’s Law slows down. Analog CMOS has power efficiency advantages over digital CMOS for low-precision applications in edge computing, scientific computing, and artificial intelligence/machine learning (AI/ML) verticals. Driven by observed non-trivial improvements in performance over digital processors while solving linear partial differential equations (PDEs), this paper presents experimental results and analysis from a single-chip CMOS analog computer for solving nonlinear PDEs. The chip integrates a 15-point fully-parallel spatially-discrete time-continuous (SDTC) finite difference time-domain (FDTD) solver for acoustic shock wave equations with radiation boundary conditions. The design was realized in TSMC 180 nm CMOS technology. It has an active area of 7.38 mm<inline-formula> <tex-math notation="LaTeX">$\times 4.64$ </tex-math></inline-formula> mm and consumes 936 mW while delivering an equivalent FDTD temporal update rate of 80 MHz and an analog bandwidth of 2 MHz. The paper discusses the challenges and associated design trade-offs in realizing such high-performance CMOS analog computers, including sensitivity to process, voltage, and temperature (PVT) variations, sensitivity to bias and voltage regulation, errors associated with noise, difficulties with calibration; it also outlines possible approaches for mitigating these challenges.https://ieeexplore.ieee.org/document/10818682/Analog computingfinite-difference time domain (FDTD)accelerationCMOSnonlinearpartial differential equations (PDEs) |
| spellingShingle | Hasantha Malavipathirana Soumyajit Mandal Nilan Udayanga Yingying Wang S. I. Hariharan Arjuna Madanayake Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip IEEE Access Analog computing finite-difference time domain (FDTD) acceleration CMOS nonlinear partial differential equations (PDEs) |
| title | Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip |
| title_full | Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip |
| title_fullStr | Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip |
| title_full_unstemmed | Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip |
| title_short | Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip |
| title_sort | analog computing for nonlinear shock tube pde models test and measurement of cmos chip |
| topic | Analog computing finite-difference time domain (FDTD) acceleration CMOS nonlinear partial differential equations (PDEs) |
| url | https://ieeexplore.ieee.org/document/10818682/ |
| work_keys_str_mv | AT hasanthamalavipathirana analogcomputingfornonlinearshocktubepdemodelstestandmeasurementofcmoschip AT soumyajitmandal analogcomputingfornonlinearshocktubepdemodelstestandmeasurementofcmoschip AT nilanudayanga analogcomputingfornonlinearshocktubepdemodelstestandmeasurementofcmoschip AT yingyingwang analogcomputingfornonlinearshocktubepdemodelstestandmeasurementofcmoschip AT sihariharan analogcomputingfornonlinearshocktubepdemodelstestandmeasurementofcmoschip AT arjunamadanayake analogcomputingfornonlinearshocktubepdemodelstestandmeasurementofcmoschip |