Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip

Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip

Long left ignored by the digital computing industry since its heyday in 1940’s, analog computing is today making a comeback as Moore’s Law slows down. Analog CMOS has power efficiency advantages over digital CMOS for low-precision applications in edge computing, scientific comp...

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Bibliographic Details
Main Authors: Hasantha Malavipathirana, Soumyajit Mandal, Nilan Udayanga, Yingying Wang, S. I. Hariharan, Arjuna Madanayake
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
Analog computing
finite-difference time domain (FDTD)
acceleration
CMOS
nonlinear
partial differential equations (PDEs)
Online Access:https://ieeexplore.ieee.org/document/10818682/
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Summary:Long left ignored by the digital computing industry since its heyday in 1940&#x2019;s, analog computing is today making a comeback as Moore&#x2019;s Law slows down. Analog CMOS has power efficiency advantages over digital CMOS for low-precision applications in edge computing, scientific computing, and artificial intelligence/machine learning (AI/ML) verticals. Driven by observed non-trivial improvements in performance over digital processors while solving linear partial differential equations (PDEs), this paper presents experimental results and analysis from a single-chip CMOS analog computer for solving nonlinear PDEs. The chip integrates a 15-point fully-parallel spatially-discrete time-continuous (SDTC) finite difference time-domain (FDTD) solver for acoustic shock wave equations with radiation boundary conditions. The design was realized in TSMC 180 nm CMOS technology. It has an active area of 7.38 mm<inline-formula> <tex-math notation="LaTeX">$\times 4.64$ </tex-math></inline-formula> mm and consumes 936 mW while delivering an equivalent FDTD temporal update rate of 80 MHz and an analog bandwidth of 2 MHz. The paper discusses the challenges and associated design trade-offs in realizing such high-performance CMOS analog computers, including sensitivity to process, voltage, and temperature (PVT) variations, sensitivity to bias and voltage regulation, errors associated with noise, difficulties with calibration; it also outlines possible approaches for mitigating these challenges.
ISSN:2169-3536

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