AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow
The increasing complexity of algorithms in embedded applications has amplified the demand for high-performance computing. Heterogeneous embedded systems, particularly FPGA-based systems-on-chip (SoCs), enhance execution speed by integrating hardware accelerator intellectual property (IP) cores. Howe...
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MDPI AG
2025-05-01
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| author | David Berrazueta-Mena Byron Navas |
| author_facet | David Berrazueta-Mena Byron Navas |
| author_sort | David Berrazueta-Mena |
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| description | The increasing complexity of algorithms in embedded applications has amplified the demand for high-performance computing. Heterogeneous embedded systems, particularly FPGA-based systems-on-chip (SoCs), enhance execution speed by integrating hardware accelerator intellectual property (IP) cores. However, traditional low-level IP-core design presents significant challenges. High-level synthesis (HLS) offers a promising alternative, enabling efficient FPGA development through high-level programming languages. Yet, effective methodologies for designing and evaluating heterogeneous FPGA-based SoCs remain crucial. This study surveys HLS tools and design concepts and presents the development of the AHA IP cores, a set of five benchmarking accelerators for rapid Zynq-based SoC evaluation. These accelerators target compute-intensive tasks, including matrix multiplication, Fast Fourier Transform (FFT), Advanced Encryption Standard (AES), Back-Propagation Neural Network (BPNN), and Artificial Neural Network (ANN). We establish a streamlined design flow using AMD-Xilinx tools for rapid prototyping and testing FPGA-based heterogeneous platforms. We outline criteria for selecting algorithms to improve speed and resource efficiency in HLS design. Our performance evaluation across various configurations highlights performance–resource trade-offs and demonstrates that ANN and BPNN achieve significant parallelism, while AES optimization increases resource utilization the most. Matrix multiplication shows strong optimization potential, whereas FFT is constrained by data dependencies. |
| format | Article |
| id | doaj-art-df80fc8d54a2479e94c278dfdee73adf |
| institution | Kabale University |
| issn | 2073-431X |
| language | English |
| publishDate | 2025-05-01 |
| publisher | MDPI AG |
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| series | Computers |
| spelling | doaj-art-df80fc8d54a2479e94c278dfdee73adf2025-08-20T03:47:53ZengMDPI AGComputers2073-431X2025-05-0114518910.3390/computers14050189AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP FlowDavid Berrazueta-Mena0Byron Navas1Departamento de Eléctrica, Electrónica y Telecomunicaciones, Universidad de las Fuerzas Armadas ESPE, Sangolqui 171103, EcuadorDepartamento de Eléctrica, Electrónica y Telecomunicaciones, Universidad de las Fuerzas Armadas ESPE, Sangolqui 171103, EcuadorThe increasing complexity of algorithms in embedded applications has amplified the demand for high-performance computing. Heterogeneous embedded systems, particularly FPGA-based systems-on-chip (SoCs), enhance execution speed by integrating hardware accelerator intellectual property (IP) cores. However, traditional low-level IP-core design presents significant challenges. High-level synthesis (HLS) offers a promising alternative, enabling efficient FPGA development through high-level programming languages. Yet, effective methodologies for designing and evaluating heterogeneous FPGA-based SoCs remain crucial. This study surveys HLS tools and design concepts and presents the development of the AHA IP cores, a set of five benchmarking accelerators for rapid Zynq-based SoC evaluation. These accelerators target compute-intensive tasks, including matrix multiplication, Fast Fourier Transform (FFT), Advanced Encryption Standard (AES), Back-Propagation Neural Network (BPNN), and Artificial Neural Network (ANN). We establish a streamlined design flow using AMD-Xilinx tools for rapid prototyping and testing FPGA-based heterogeneous platforms. We outline criteria for selecting algorithms to improve speed and resource efficiency in HLS design. Our performance evaluation across various configurations highlights performance–resource trade-offs and demonstrates that ANN and BPNN achieve significant parallelism, while AES optimization increases resource utilization the most. Matrix multiplication shows strong optimization potential, whereas FFT is constrained by data dependencies.https://www.mdpi.com/2073-431X/14/5/189accelerator architecturesbenchmarkdesign automationembedded systemsFPGA-based acceleratorheterogeneous systems |
| spellingShingle | David Berrazueta-Mena Byron Navas AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow Computers accelerator architectures benchmark design automation embedded systems FPGA-based accelerator heterogeneous systems |
| title | AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow |
| title_full | AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow |
| title_fullStr | AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow |
| title_full_unstemmed | AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow |
| title_short | AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow |
| title_sort | aha design and evaluation of compute intensive hardware accelerators for amd xilinx zynq socs using hls ip flow |
| topic | accelerator architectures benchmark design automation embedded systems FPGA-based accelerator heterogeneous systems |
| url | https://www.mdpi.com/2073-431X/14/5/189 |
| work_keys_str_mv | AT davidberrazuetamena ahadesignandevaluationofcomputeintensivehardwareacceleratorsforamdxilinxzynqsocsusinghlsipflow AT byronnavas ahadesignandevaluationofcomputeintensivehardwareacceleratorsforamdxilinxzynqsocsusinghlsipflow |