Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories
While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10412202/ |
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| _version_ | 1841526375281852416 |
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| author | Piyush Kumar Da Eun Shim Siri Narla Azad Naeemi |
| author_facet | Piyush Kumar Da Eun Shim Siri Narla Azad Naeemi |
| author_sort | Piyush Kumar |
| collection | DOAJ |
| description | While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we first study the impact of shrunk interconnect dimensions on MRAM performance at various technology nodes. Then, we investigate the impact of various potential back-end-of-the-line (BEOL) technology solutions at the 7 nm node. Based on interconnect resistance values from technology computer-aided design (TCAD) simulations and MRAM device characteristics from experimentally validated/calibrated physical models, we quantify the potential array-level performance of MRAM using SPICE simulations. We project that some potential BEOL technology solutions can reduce the write energy by up to 34.6% with spin–orbit torque (SOT) MRAM and 29.0% with spin-transfer torque (STT) MRAM. We also observe up to 21.4% reduction in the read energy of the SOT-MRAM arrays. |
| format | Article |
| id | doaj-art-c57ce292b48d402b8edde7ca486724fd |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-c57ce292b48d402b8edde7ca486724fd2025-01-17T00:00:28ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-0110132110.1109/JXCDC.2024.335762510412202Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access MemoriesPiyush Kumar0https://orcid.org/0000-0003-0760-7166Da Eun Shim1Siri Narla2https://orcid.org/0000-0003-0039-9026Azad Naeemi3https://orcid.org/0000-0003-4774-9046School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USASchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USASchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USASchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USAWhile magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we first study the impact of shrunk interconnect dimensions on MRAM performance at various technology nodes. Then, we investigate the impact of various potential back-end-of-the-line (BEOL) technology solutions at the 7 nm node. Based on interconnect resistance values from technology computer-aided design (TCAD) simulations and MRAM device characteristics from experimentally validated/calibrated physical models, we quantify the potential array-level performance of MRAM using SPICE simulations. We project that some potential BEOL technology solutions can reduce the write energy by up to 34.6% with spin–orbit torque (SOT) MRAM and 29.0% with spin-transfer torque (STT) MRAM. We also observe up to 21.4% reduction in the read energy of the SOT-MRAM arrays.https://ieeexplore.ieee.org/document/10412202/Back-end-of-the-line (BEOL)interconnectmagnetic random-access memory (MRAM)spin-orbit torque (SOT)spin-transfer torque (STT) |
| spellingShingle | Piyush Kumar Da Eun Shim Siri Narla Azad Naeemi Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Back-end-of-the-line (BEOL) interconnect magnetic random-access memory (MRAM) spin-orbit torque (SOT) spin-transfer torque (STT) |
| title | Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories |
| title_full | Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories |
| title_fullStr | Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories |
| title_full_unstemmed | Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories |
| title_short | Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories |
| title_sort | impact of technology scaling and back end of the line technology solutions on magnetic random access memories |
| topic | Back-end-of-the-line (BEOL) interconnect magnetic random-access memory (MRAM) spin-orbit torque (SOT) spin-transfer torque (STT) |
| url | https://ieeexplore.ieee.org/document/10412202/ |
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