Implementation and comprehensive investigation of gate engineered Si0.1Ge0.9/GaAs charged plasma based JLTFET for improved analog/ RF performance - Pranita Soni; Aditya Jain; Kaushal Kumar; Lokesh Kumar Soni; Ajay Kumar; Neha Gupta; Amit Kumar Goyal; Rakesh Saroha (Results in Engineering)
This study introduces the Variable Length Dual Dielectric Material-Gate Spacer Engineering Heterostructure Junction-Less Tunnel Field-Effect Transistor (VLDD-GSE-HJLTFET), a novel device that integrates advanced bandgap engineering, dual-dielectric gate configuration, and heterostructure design using Si0.1Ge0.9/GaAs layers. The device employs variable region lengths, with a longer channel relative to the source and drain, to effectively mitigate short-channel effects. Key findings reveal that the VLDD-GSE-HJLTFET achieves ION ∼285 µA, which is four times higher than VLSD-GSE-HJLTFET (Variable Length Single Dielectric GSE-HJLTFET), with an ION/IOFF ratio improved by 2.8 times. The subthreshold swing (SS) is below 60 mV/decade, marking a 3 times improvement, while the threshold voltage (Vth) is 16.86 % and 28.06 % lower compared to VLSD-GSE-HJLTFET and Con-Si-JLTFET, respectively. For RF performance, the device demonstrates a 115 % higher cutoff frequency, 540 improvements in gain bandwidth product, and 2.67 times and 7.7 times faster intrinsic delay compared to VLSD-GSE-HJLTFET and Con-Si-JLTFET, respectively. Enhanced gate capacitances and superior intercept points further validate its suitability for high-frequency and low-power applications. The novelty lies in combining dual-dielectric spacer engineering, heterostructure material optimization, and a variable length configuration, establishing VLDD-GSE-HJLTFET as a breakthrough in low-power, high-frequency device design.