Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines
As semiconductor devices become smaller, their performance and integration density improve, but new negative effects emerge due to the reduced distance between structures. In DRAM, these effects can lead to data loss or require additional refresh cycles, causing performance degradation. Specifically...
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MDPI AG
2024-11-01
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| author | Yeongmyeong Cho Yeon-Seok Kim Min-Woo Kwon |
| author_facet | Yeongmyeong Cho Yeon-Seok Kim Min-Woo Kwon |
| author_sort | Yeongmyeong Cho |
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| description | As semiconductor devices become smaller, their performance and integration density improve, but new negative effects emerge due to the reduced distance between structures. In DRAM, these effects can lead to data loss or require additional refresh cycles, causing performance degradation. Specifically, in the 6F<sup>2</sup> DRAM structure, activating a word line (WL) lowers the energy barrier of adjacent WLs, leading to the Pass Gate Effect (PGE). This study investigates the use of buried oxide beneath the WL to mitigate the PGE through simulation. Using SILVACO TCAD, we analyzed the impact of varying the size and position of the buried oxide on the PGE. The results showed that increasing the oxide size or reducing the distance to the WL effectively reduced the PGE. However, the presence of interface traps, which increase with the addition of buried oxide, was found to exacerbate the PGE, indicating that minimizing interface traps is crucial when incorporating buried oxide. |
| format | Article |
| id | doaj-art-be48fcdd13e34a5dae1e52cc5cb14c96 |
| institution | Kabale University |
| issn | 2076-3417 |
| language | English |
| publishDate | 2024-11-01 |
| publisher | MDPI AG |
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| series | Applied Sciences |
| spelling | doaj-art-be48fcdd13e34a5dae1e52cc5cb14c962024-11-26T17:48:25ZengMDPI AGApplied Sciences2076-34172024-11-0114221034810.3390/app142210348Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word LinesYeongmyeong Cho0Yeon-Seok Kim1Min-Woo Kwon2Department of Electronic Engineering, Gangneung-Wonju National University, Gangneung 25457, Republic of KoreaDepartment of Electronic Engineering, Gangneung-Wonju National University, Gangneung 25457, Republic of KoreaDepartment of Electronic Engineering, Seoul National University of Science and Technology, Seoul 01811, Republic of KoreaAs semiconductor devices become smaller, their performance and integration density improve, but new negative effects emerge due to the reduced distance between structures. In DRAM, these effects can lead to data loss or require additional refresh cycles, causing performance degradation. Specifically, in the 6F<sup>2</sup> DRAM structure, activating a word line (WL) lowers the energy barrier of adjacent WLs, leading to the Pass Gate Effect (PGE). This study investigates the use of buried oxide beneath the WL to mitigate the PGE through simulation. Using SILVACO TCAD, we analyzed the impact of varying the size and position of the buried oxide on the PGE. The results showed that increasing the oxide size or reducing the distance to the WL effectively reduced the PGE. However, the presence of interface traps, which increase with the addition of buried oxide, was found to exacerbate the PGE, indicating that minimizing interface traps is crucial when incorporating buried oxide.https://www.mdpi.com/2076-3417/14/22/10348buried oxidePGE (Pass Gate Effect)DRAM (Dynamic Random Access Memory)BCAT (Buried Channel Array Transistor)TCAD simulation |
| spellingShingle | Yeongmyeong Cho Yeon-Seok Kim Min-Woo Kwon Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines Applied Sciences buried oxide PGE (Pass Gate Effect) DRAM (Dynamic Random Access Memory) BCAT (Buried Channel Array Transistor) TCAD simulation |
| title | Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines |
| title_full | Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines |
| title_fullStr | Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines |
| title_full_unstemmed | Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines |
| title_short | Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines |
| title_sort | mitigating pass gate effect in buried channel array transistors through buried oxide integration addressing interference phenomenon between word lines |
| topic | buried oxide PGE (Pass Gate Effect) DRAM (Dynamic Random Access Memory) BCAT (Buried Channel Array Transistor) TCAD simulation |
| url | https://www.mdpi.com/2076-3417/14/22/10348 |
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