Renlong, Y., Qiong, Z., Haitao, H., Yujun, W., & Enlei, L. Design and realization of a high-speed traffic collection and processing scheme for campus networks using FPGA. Editorial Department of Journal on Communications.
Chicago Style (17th ed.) CitationRenlong, YAO, ZHAO Qiong, HE Haitao, WEI Yujun, and LI Enlei. Design and Realization of a High-speed Traffic Collection and Processing Scheme for Campus Networks Using FPGA. Editorial Department of Journal on Communications.
MLA (9th ed.) CitationRenlong, YAO, et al. Design and Realization of a High-speed Traffic Collection and Processing Scheme for Campus Networks Using FPGA. Editorial Department of Journal on Communications.
Warning: These citations may not always be 100% accurate.