Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques

Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques

Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementatio...

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Bibliographic Details
Main Authors: Agfianto Eko Putra, Oskar Natan, Jazi Eko Istiyanto
Format: Article
Language:English
Published: IIUM Press, International Islamic University Malaysia 2025-01-01
Series:International Islamic University Malaysia Engineering Journal
Subjects:
sha-3
FPGA
dsp48
pipeline
Online Access:https://journals.iium.edu.my/ejournal/index.php/iiumej/article/view/3328
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