Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques
Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementatio...
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IIUM Press, International Islamic University Malaysia
2025-01-01
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| Series: | International Islamic University Malaysia Engineering Journal |
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| Online Access: | https://journals.iium.edu.my/ejournal/index.php/iiumej/article/view/3328 |
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| author | Agfianto Eko Putra Oskar Natan Jazi Eko Istiyanto |
| author_facet | Agfianto Eko Putra Oskar Natan Jazi Eko Istiyanto |
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Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), and Buffer (BUFG). The system's highest frequency is 107.979 MHz, achieving different throughputs for cryptographic hash functions. Specifically, it performs a throughput of 5.183 Gbps for SHA3-224, 4.895 Gbps for SHA3-256, 3.743 Gbps for SHA3-384, and 2.591 Gbps for SHA3-512.
ABSTRAK: Menggunakan SHA-3 pada peranti FPGA memerlukan peruntukan sumber yang ketara, walaupun daya pengeluaran yang terhasil adalah terhad. Untuk menangani isu ini, kajian ini menggunakan modul DSP48 yang disertakan pada Xilinx FPGA dan melaksanakan metodologi saluran paip lapan peringkat untuk meminimumkan kependaman. Reka bentuk pelaksanaan terdiri daripada laluan data dan modul pengawal, menggunakan siri FPGA Xilinx Artix-7-100T sebagai perkakasan. Kaedah ini menggunakan sumber FPGA seperti Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), dan Penampan (BUFG). Kekerapan tertinggi sistem ialah 107.979 MHz, dan ia mencapai daya pemprosesan yang berbeza untuk fungsi cincang kriptografi yang berbeza. Secara khususnya, ia mencapai daya pemprosesan 5.183 Gbps untuk SHA3-224, 4.895 Gbps untuk SHA3-256, 3.743 Gbps untuk SHA3-384 dan 2.591 Gbps untuk SHA3-512.
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| format | Article |
| id | doaj-art-b9cca29bd44441cdb2ebf90f7b146ff6 |
| institution | Kabale University |
| issn | 1511-788X 2289-7860 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IIUM Press, International Islamic University Malaysia |
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| series | International Islamic University Malaysia Engineering Journal |
| spelling | doaj-art-b9cca29bd44441cdb2ebf90f7b146ff62025-01-10T12:40:40ZengIIUM Press, International Islamic University MalaysiaInternational Islamic University Malaysia Engineering Journal1511-788X2289-78602025-01-0126110.31436/iiumej.v26i1.3328Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining TechniquesAgfianto Eko Putra0https://orcid.org/0000-0002-1568-6864Oskar Natan1https://orcid.org/0000-0003-3896-0448Jazi Eko Istiyanto2https://orcid.org/0009-0000-5670-6481Universitas Gadjah Mada Universitas Gadjah Mada Universitas Gadjah Mada Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), and Buffer (BUFG). The system's highest frequency is 107.979 MHz, achieving different throughputs for cryptographic hash functions. Specifically, it performs a throughput of 5.183 Gbps for SHA3-224, 4.895 Gbps for SHA3-256, 3.743 Gbps for SHA3-384, and 2.591 Gbps for SHA3-512. ABSTRAK: Menggunakan SHA-3 pada peranti FPGA memerlukan peruntukan sumber yang ketara, walaupun daya pengeluaran yang terhasil adalah terhad. Untuk menangani isu ini, kajian ini menggunakan modul DSP48 yang disertakan pada Xilinx FPGA dan melaksanakan metodologi saluran paip lapan peringkat untuk meminimumkan kependaman. Reka bentuk pelaksanaan terdiri daripada laluan data dan modul pengawal, menggunakan siri FPGA Xilinx Artix-7-100T sebagai perkakasan. Kaedah ini menggunakan sumber FPGA seperti Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), dan Penampan (BUFG). Kekerapan tertinggi sistem ialah 107.979 MHz, dan ia mencapai daya pemprosesan yang berbeza untuk fungsi cincang kriptografi yang berbeza. Secara khususnya, ia mencapai daya pemprosesan 5.183 Gbps untuk SHA3-224, 4.895 Gbps untuk SHA3-256, 3.743 Gbps untuk SHA3-384 dan 2.591 Gbps untuk SHA3-512. https://journals.iium.edu.my/ejournal/index.php/iiumej/article/view/3328sha-3FPGAdsp48pipeline |
| spellingShingle | Agfianto Eko Putra Oskar Natan Jazi Eko Istiyanto Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques International Islamic University Malaysia Engineering Journal sha-3 FPGA dsp48 pipeline |
| title | Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques |
| title_full | Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques |
| title_fullStr | Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques |
| title_full_unstemmed | Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques |
| title_short | Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques |
| title_sort | optimizing fpga resource allocation for sha 3 using dsp48 and pipelining techniques |
| topic | sha-3 FPGA dsp48 pipeline |
| url | https://journals.iium.edu.my/ejournal/index.php/iiumej/article/view/3328 |
| work_keys_str_mv | AT agfiantoekoputra optimizingfpgaresourceallocationforsha3usingdsp48andpipeliningtechniques AT oskarnatan optimizingfpgaresourceallocationforsha3usingdsp48andpipeliningtechniques AT jaziekoistiyanto optimizingfpgaresourceallocationforsha3usingdsp48andpipeliningtechniques |