Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation - Sa'ed Abed; Reem Jaffal; Bassam Jamil Mohd; Mohammad Alshayeji (IET Circuits, Devices and Systems)
Abstract Information security is essential to ensure security of exchanged sensitive data in resource‐constrained devices (RCDs) because they are used widely in the Internet of things (IoT). The implementation of special ciphers is required in these RCDs, as they have many limitations and constraints, such as low power/energy dissipation, and require low hardware resources. The SM4 cipher is one of the common block ciphers, which can be easily implemented and offers a high level of security. The objective of this study is to determine the optimum field‐programmable gate array (FPGA) design for SM4 to facilitate reconfiguring the FPGA with an optimum design during operation. Various FPGA design options for SM4 ciphers are examined, and the performance metrics are modeled: power, energy, area, and speed. Scalar and pipelined designs with one or multiple hardware rounds are considered without altering the cipher algorithm. The results show that the best scalar implementation utilises less resources than the pipelined implementations by 7%. Alternatively, pipelined implementations perform better regarding speed and energy dissipation by 10 times and 40% of the scalar implementation, respectively. The pipeline implementations with eight or 16 rounds are optimum for continuous streams of data, and the two‐round design is the optimum design across ciphers.