VLSI implementation of AES algorithm against differential power attack and differential fault attack
A VLSI implementation of AES algorithm against both differential power attack and differential fault attack was proposed. The main countermeasures employed in this hardware design are masking technique and two-dimensional parity-based concurrent error detection method. And exploits such methods as s...
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| Format: | Article |
| Language: | zho |
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Editorial Department of Journal on Communications
2010-01-01
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| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/zh/article/74650743/ |
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| _version_ | 1841537689671696384 |
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| author | HAN Jun ZENG Xiao-yang ZHAO Jia |
| author_facet | HAN Jun ZENG Xiao-yang ZHAO Jia |
| author_sort | HAN Jun |
| collection | DOAJ |
| description | A VLSI implementation of AES algorithm against both differential power attack and differential fault attack was proposed. The main countermeasures employed in this hardware design are masking technique and two-dimensional parity-based concurrent error detection method. And exploits such methods as separating 128bit calculation into four 32bit calculations, module reuse and optimization of calculation order was exploited to reduce hardware cost. Moreover, a 3 level pipelined structure of AES encryption and decryption is used to improve hardware speed and throughput. The AES IP core based on these techniques can resist two kinds of side channel attacks with reasonable performance and cost. |
| format | Article |
| id | doaj-art-ad25ec942f5b4fcd80092e7f9245dd2b |
| institution | Kabale University |
| issn | 1000-436X |
| language | zho |
| publishDate | 2010-01-01 |
| publisher | Editorial Department of Journal on Communications |
| record_format | Article |
| series | Tongxin xuebao |
| spelling | doaj-art-ad25ec942f5b4fcd80092e7f9245dd2b2025-01-14T08:26:58ZzhoEditorial Department of Journal on CommunicationsTongxin xuebao1000-436X2010-01-0131202974650743VLSI implementation of AES algorithm against differential power attack and differential fault attackHAN JunZENG Xiao-yangZHAO JiaA VLSI implementation of AES algorithm against both differential power attack and differential fault attack was proposed. The main countermeasures employed in this hardware design are masking technique and two-dimensional parity-based concurrent error detection method. And exploits such methods as separating 128bit calculation into four 32bit calculations, module reuse and optimization of calculation order was exploited to reduce hardware cost. Moreover, a 3 level pipelined structure of AES encryption and decryption is used to improve hardware speed and throughput. The AES IP core based on these techniques can resist two kinds of side channel attacks with reasonable performance and cost.http://www.joconline.com.cn/zh/article/74650743/information securityanti-attack algorithmVLSI implementationside channel attackAES |
| spellingShingle | HAN Jun ZENG Xiao-yang ZHAO Jia VLSI implementation of AES algorithm against differential power attack and differential fault attack Tongxin xuebao information security anti-attack algorithm VLSI implementation side channel attack AES |
| title | VLSI implementation of AES algorithm against differential power attack and differential fault attack |
| title_full | VLSI implementation of AES algorithm against differential power attack and differential fault attack |
| title_fullStr | VLSI implementation of AES algorithm against differential power attack and differential fault attack |
| title_full_unstemmed | VLSI implementation of AES algorithm against differential power attack and differential fault attack |
| title_short | VLSI implementation of AES algorithm against differential power attack and differential fault attack |
| title_sort | vlsi implementation of aes algorithm against differential power attack and differential fault attack |
| topic | information security anti-attack algorithm VLSI implementation side channel attack AES |
| url | http://www.joconline.com.cn/zh/article/74650743/ |
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