A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation
Scan-based side-channel attacks have been proven to be popular attack methods against cryptographic chips. In these attacks, attackers can use scan chains inside a chip to obtain internal sensitive information of the chip, such as crypto key or other secret data. To counteract scan-based side-channe...
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| Format: | Article |
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IEEE
2024-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10767141/ |
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| _version_ | 1841533431589109760 |
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| author | Weizheng Wang Xingxing Gong Shuo Cai Jiamin Liu Xiangqi Wang |
| author_facet | Weizheng Wang Xingxing Gong Shuo Cai Jiamin Liu Xiangqi Wang |
| author_sort | Weizheng Wang |
| collection | DOAJ |
| description | Scan-based side-channel attacks have been proven to be popular attack methods against cryptographic chips. In these attacks, attackers can use scan chains inside a chip to obtain internal sensitive information of the chip, such as crypto key or other secret data. To counteract scan-based side-channel attacks, various secure strategies have been put forward by researchers, but they generally exist some flaws. In this paper, we propose a low overhead secure scan design based on scan obfuscation. In this method, to increase the security of the design, we insert a set of fuse-antifuse cells (CF) controlled by the obfuscation key between the scan flip flops (SFF) and add a controller at the scan-out port. The undisturbed scan test can be launched only when both the correct test key and obfuscation key are delivered. Simulation results and theoretical analysis show that the scheme effectively thwarts scan-based attacks while maintaining minimal area overhead and high testability. In the case of a pipelined AES circuit, with a total test key and obfuscation key length of 128, the area overhead is as low as 0.07%, and the probability of a successful brute-force attack is only <inline-formula> <tex-math notation="LaTeX">$2.9\times 10 ^{-39}$ </tex-math></inline-formula>. |
| format | Article |
| id | doaj-art-acb0893b3cce46718ebd5cd7ee50c0a4 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-acb0893b3cce46718ebd5cd7ee50c0a42025-01-16T00:01:58ZengIEEEIEEE Access2169-35362024-01-011218256118257010.1109/ACCESS.2024.350589810767141A Low-Overhead and High-Security Scan Design Based on Scan ObfuscationWeizheng Wang0https://orcid.org/0000-0001-7031-365XXingxing Gong1https://orcid.org/0009-0008-3600-4835Shuo Cai2Jiamin Liu3Xiangqi Wang4https://orcid.org/0009-0008-5008-2573College of Information Science and Engineering, Hunan Women’s University, Changsha, ChinaSchool of Computer and Communication Engineering, Changsha University of Science and Technology, Changsha, ChinaSchool of Computer and Communication Engineering, Changsha University of Science and Technology, Changsha, ChinaCollege of Information Science and Engineering, Hunan Women’s University, Changsha, ChinaSchool of Mathematics and Statistics, Hunan First Normal University, Changsha, ChinaScan-based side-channel attacks have been proven to be popular attack methods against cryptographic chips. In these attacks, attackers can use scan chains inside a chip to obtain internal sensitive information of the chip, such as crypto key or other secret data. To counteract scan-based side-channel attacks, various secure strategies have been put forward by researchers, but they generally exist some flaws. In this paper, we propose a low overhead secure scan design based on scan obfuscation. In this method, to increase the security of the design, we insert a set of fuse-antifuse cells (CF) controlled by the obfuscation key between the scan flip flops (SFF) and add a controller at the scan-out port. The undisturbed scan test can be launched only when both the correct test key and obfuscation key are delivered. Simulation results and theoretical analysis show that the scheme effectively thwarts scan-based attacks while maintaining minimal area overhead and high testability. In the case of a pipelined AES circuit, with a total test key and obfuscation key length of 128, the area overhead is as low as 0.07%, and the probability of a successful brute-force attack is only <inline-formula> <tex-math notation="LaTeX">$2.9\times 10 ^{-39}$ </tex-math></inline-formula>.https://ieeexplore.ieee.org/document/10767141/Cryptographic chipsdesign for testabilityscan obfuscationscan-based side-channel attacks |
| spellingShingle | Weizheng Wang Xingxing Gong Shuo Cai Jiamin Liu Xiangqi Wang A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation IEEE Access Cryptographic chips design for testability scan obfuscation scan-based side-channel attacks |
| title | A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation |
| title_full | A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation |
| title_fullStr | A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation |
| title_full_unstemmed | A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation |
| title_short | A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation |
| title_sort | low overhead and high security scan design based on scan obfuscation |
| topic | Cryptographic chips design for testability scan obfuscation scan-based side-channel attacks |
| url | https://ieeexplore.ieee.org/document/10767141/ |
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