Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA
<p>In this research, a 16-bit multi-mode second-order Delta-Sigma Modulator-Digital-to-Analog Converter (DSM-DAC) with a time-interleaved (TI) structure operating at a center frequency of 4 GHz and a bandwidth of 20 MHz has been implemented using VHDL on an FPGA platform. The proposed architec...
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Islamic Azad University Bushehr Branch
2025-01-01
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| Series: | مهندسی مخابرات جنوب |
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| Online Access: | https://sanad.iau.ir/journal/jce/Article/1105014 |
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| author | Abolfazl Roshanpanah Pooya Torkzadeh Khosrow Hajsadeghi Massoud Dousti |
| author_facet | Abolfazl Roshanpanah Pooya Torkzadeh Khosrow Hajsadeghi Massoud Dousti |
| author_sort | Abolfazl Roshanpanah |
| collection | DOAJ |
| description | <p>In this research, a 16-bit multi-mode second-order Delta-Sigma Modulator-Digital-to-Analog Converter (DSM-DAC) with a time-interleaved (TI) structure operating at a center frequency of 4 GHz and a bandwidth of 20 MHz has been implemented using VHDL on an FPGA platform. The proposed architecture utilizes a single clock frequency for generating RF signals. The second-order DSM is reconfigurable, offering three filter modes: LP, BP at Fs/4, and HP for signal synthesis. Since the coefficients remain simple for all modes, multiplication operations can be achieved using a shifter block. To investigate the effect of duty-cycle-error (DCE) and its compensation, various error values are applied to the modulator and compensation is performed. A novel solution is proposed to overcome the DCE by adjusting the filter and unilaterally narrowing the signal passband without adding extra hardware complexity. This approach significantly enhances the SNDR and SFDR of the DSM output, even for the BP mode. Another challenge is the mismatch error in DAC cells. This error is simulated and compensated using two methods: DWA and SDEM. Simulation results in ISE demonstrate that the SNDR values for LP, BP, and HP modes are 106.10, 105.65, and 104.95 dB, respectively.</p> |
| format | Article |
| id | doaj-art-a967f27d935e4daa87b4a1e6e3cca661 |
| institution | Kabale University |
| issn | 2980-9231 |
| language | fas |
| publishDate | 2025-01-01 |
| publisher | Islamic Azad University Bushehr Branch |
| record_format | Article |
| series | مهندسی مخابرات جنوب |
| spelling | doaj-art-a967f27d935e4daa87b4a1e6e3cca6612025-01-11T05:06:08ZfasIslamic Azad University Bushehr Branchمهندسی مخابرات جنوب2980-92312025-01-01145493117Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGAAbolfazl Roshanpanah0Pooya Torkzadeh1Khosrow Hajsadeghi2Massoud Dousti3PhD Student, Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, IranDepartment of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, IranAssociate Professor, Department of Electrical Engineering, Sharif University of Technology, Tehran, IranDepartment of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran<p>In this research, a 16-bit multi-mode second-order Delta-Sigma Modulator-Digital-to-Analog Converter (DSM-DAC) with a time-interleaved (TI) structure operating at a center frequency of 4 GHz and a bandwidth of 20 MHz has been implemented using VHDL on an FPGA platform. The proposed architecture utilizes a single clock frequency for generating RF signals. The second-order DSM is reconfigurable, offering three filter modes: LP, BP at Fs/4, and HP for signal synthesis. Since the coefficients remain simple for all modes, multiplication operations can be achieved using a shifter block. To investigate the effect of duty-cycle-error (DCE) and its compensation, various error values are applied to the modulator and compensation is performed. A novel solution is proposed to overcome the DCE by adjusting the filter and unilaterally narrowing the signal passband without adding extra hardware complexity. This approach significantly enhances the SNDR and SFDR of the DSM output, even for the BP mode. Another challenge is the mismatch error in DAC cells. This error is simulated and compensated using two methods: DWA and SDEM. Simulation results in ISE demonstrate that the SNDR values for LP, BP, and HP modes are 106.10, 105.65, and 104.95 dB, respectively.</p>https://sanad.iau.ir/journal/jce/Article/1105014delta-sigma modulator duty-cycle-error error-feedback fpga mismatch time-interleaved |
| spellingShingle | Abolfazl Roshanpanah Pooya Torkzadeh Khosrow Hajsadeghi Massoud Dousti Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA مهندسی مخابرات جنوب delta-sigma modulator duty-cycle-error error-feedback fpga mismatch time-interleaved |
| title | Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA |
| title_full | Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA |
| title_fullStr | Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA |
| title_full_unstemmed | Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA |
| title_short | Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA |
| title_sort | design and implementation of a 16 bit multi mode delta sigma digital to analog converter with time interleaved structure multi channel and compensation of non idealities based on fpga |
| topic | delta-sigma modulator duty-cycle-error error-feedback fpga mismatch time-interleaved |
| url | https://sanad.iau.ir/journal/jce/Article/1105014 |
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