Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer
In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approx...
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MDPI AG
2024-11-01
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| author | Britto Pari James Leung Man-Fai Mariammal Karuthapandian Vaithiyanathan Dhandapani |
| author_facet | Britto Pari James Leung Man-Fai Mariammal Karuthapandian Vaithiyanathan Dhandapani |
| author_sort | Britto Pari James |
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| description | In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore, the input stream is truncated with an erratum mending unit to roughly construct the partial products. For an aggregation of PPs, an approximate Wallace tree is taken into consideration to further minimize hardware expenses. Consequently, the suggested design’s latency, utilized area, and power usage are largely reduced. The Xilinx Vertex device is expedited, given the synthesis of the suggested multichannel realization with 16 taps, which is simulated using the Verilog formulary. It is observed that the filter structure with one channel produced the desired results, and the system’s frequency can support up to 429 MHz with a reduced area. Utilizing TSMC 180 nm CMOS technology and the Cadence RC compiler, cell-level performance is also achieved. |
| format | Article |
| id | doaj-art-a7a6e5603b9748f3badfc7b8fcac8cef |
| institution | Kabale University |
| issn | 1424-8220 |
| language | English |
| publishDate | 2024-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj-art-a7a6e5603b9748f3badfc7b8fcac8cef2024-11-26T18:20:53ZengMDPI AGSensors1424-82202024-11-012422714910.3390/s24227149Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-MultiplexerBritto Pari James0Leung Man-Fai1Mariammal Karuthapandian2Vaithiyanathan Dhandapani3Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai 600062, IndiaSchool of Computing and Information Science, Faculty of Science and Engineering, Anglia Ruskin University, Cambridge CB1 1PT, UKMadras Institute of Technology, Anna University, Chennai 600044, IndiaNational Institute of Technology Delhi, Delhi 110036, IndiaIn this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore, the input stream is truncated with an erratum mending unit to roughly construct the partial products. For an aggregation of PPs, an approximate Wallace tree is taken into consideration to further minimize hardware expenses. Consequently, the suggested design’s latency, utilized area, and power usage are largely reduced. The Xilinx Vertex device is expedited, given the synthesis of the suggested multichannel realization with 16 taps, which is simulated using the Verilog formulary. It is observed that the filter structure with one channel produced the desired results, and the system’s frequency can support up to 429 MHz with a reduced area. Utilizing TSMC 180 nm CMOS technology and the Cadence RC compiler, cell-level performance is also achieved.https://www.mdpi.com/1424-8220/24/22/7149distributed arithmeticfinite impulse response filterapproximate computingFPGAmultiply-accumulate unithardware optimization |
| spellingShingle | Britto Pari James Leung Man-Fai Mariammal Karuthapandian Vaithiyanathan Dhandapani Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer Sensors distributed arithmetic finite impulse response filter approximate computing FPGA multiply-accumulate unit hardware optimization |
| title | Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer |
| title_full | Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer |
| title_fullStr | Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer |
| title_full_unstemmed | Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer |
| title_short | Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer |
| title_sort | delineation of optimized single and multichannel approximate da based filter design using influential single mac strategy for trans multiplexer |
| topic | distributed arithmetic finite impulse response filter approximate computing FPGA multiply-accumulate unit hardware optimization |
| url | https://www.mdpi.com/1424-8220/24/22/7149 |
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