An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K - Hafeez Raza; Shivendra Singh Parihar; Yogesh Singh Chauhan; Hussam Amrouch; Avinash Lahgere (IEEE Journal on Exploratory Solid-State Computational Devices and Circuits)
In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum operating voltage ( $V_{\min }$ ) of 5-nm Fin Field-Effect Transistors (FinFETs)-based Static Random Access Memory (SRAM) cells. To perform the SRAM $V_{\min }$ evaluation, we have measured the FinFETs fabricated using a commercial 5-nm technology down to 10 K. Next, we calibrate a cryogenic-aware BSIM-CMG FinFET compact model, which we use with our SRAM evaluation framework. For a comprehensive study, we evaluate three industry-standard SRAM cell types: 1) high-density cell (HDC); 2) low-voltage cell (LVC); and 3) high-performance cell (HPC). We analyze the impact of the threshold voltage ( $V_{\text {TH}}$ ) and gate length ( $L_{G}$ )-only variations on the SRAM noise resilience. At cryogenic temperature, minimum read voltage ( $V_{\min ,R}$ ) =0.15 V (62% decrease from room temperature) and minimum write voltage ( $V_{\min ,W}$ ) =0.45 V are achieved without read-/write-assist circuits. We also highlight that the LVC provides the best tradeoff for $V_{\min }$ between read and write operations for low-power cryogenic applications.