Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors
We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb...
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IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10409158/ |
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| author | Gautham Rangasamy Zhongyunshen Zhu Lars-Erik Wernersson |
| author_facet | Gautham Rangasamy Zhongyunshen Zhu Lars-Erik Wernersson |
| author_sort | Gautham Rangasamy |
| collection | DOAJ |
| description | We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb source segments improved the transistor metrics (subthreshold swing (SS) and the on-current performance), due to the formation of a nid-InAsSb segment. The devices display a minimum SS of 26 mV/dec and on-current of <inline-formula> <tex-math notation="LaTeX">$10.2 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">$V_{\text {DS}}$ </tex-math></inline-formula> of 300 mV. The performance of devices were improved further by optimizing the doping levels which led to record subthermal current of <inline-formula> <tex-math notation="LaTeX">$1.2 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and transconductance of <inline-formula> <tex-math notation="LaTeX">$205 ~\mu \text{S}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">$V_{\text {DS}}$ </tex-math></inline-formula> of 500 mV. |
| format | Article |
| id | doaj-art-a408c070e7b04b6c926ef356cd5dd6b0 |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-a408c070e7b04b6c926ef356cd5dd6b02025-01-17T00:00:31ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-011081210.1109/JXCDC.2024.335594910409158Source Design of Vertical III–V Nanowire Tunnel Field-Effect TransistorsGautham Rangasamy0https://orcid.org/0000-0003-0074-3210Zhongyunshen Zhu1https://orcid.org/0000-0002-7588-4088Lars-Erik Wernersson2https://orcid.org/0000-0002-1039-5849Department of Electrical and Information Technology, Lund University, Lund, SwedenDepartment of Electrical and Information Technology, Lund University, Lund, SwedenDepartment of Electrical and Information Technology, Lund University, Lund, SwedenWe systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb source segments improved the transistor metrics (subthreshold swing (SS) and the on-current performance), due to the formation of a nid-InAsSb segment. The devices display a minimum SS of 26 mV/dec and on-current of <inline-formula> <tex-math notation="LaTeX">$10.2 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">$V_{\text {DS}}$ </tex-math></inline-formula> of 300 mV. The performance of devices were improved further by optimizing the doping levels which led to record subthermal current of <inline-formula> <tex-math notation="LaTeX">$1.2 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and transconductance of <inline-formula> <tex-math notation="LaTeX">$205 ~\mu \text{S}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">$V_{\text {DS}}$ </tex-math></inline-formula> of 500 mV.https://ieeexplore.ieee.org/document/10409158/III-Vsource engineeringsteep-slopetunnel field-effect transistors (TFETs)vertical nanowires |
| spellingShingle | Gautham Rangasamy Zhongyunshen Zhu Lars-Erik Wernersson Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors IEEE Journal on Exploratory Solid-State Computational Devices and Circuits III-V source engineering steep-slope tunnel field-effect transistors (TFETs) vertical nanowires |
| title | Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors |
| title_full | Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors |
| title_fullStr | Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors |
| title_full_unstemmed | Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors |
| title_short | Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors |
| title_sort | source design of vertical iii x2013 v nanowire tunnel field effect transistors |
| topic | III-V source engineering steep-slope tunnel field-effect transistors (TFETs) vertical nanowires |
| url | https://ieeexplore.ieee.org/document/10409158/ |
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