Modeling the interrupt transmission process of SR-IOV cryptographic device
The SR-IOV cryptographic device generates a large number of I/O interrupts when performing operations in a virtualized environment,causing the CPU to frequently switch between the Root mode and the Non-Root mode,which brings huge system performance overhead and affects the operational performance of...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
POSTS&TELECOM PRESS Co., LTD
2019-02-01
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| Series: | 网络与信息安全学报 |
| Subjects: | |
| Online Access: | http://www.cjnis.com.cn/thesisDetails#10.11959/j.issn.2096-109x.2019007 |
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| Summary: | The SR-IOV cryptographic device generates a large number of I/O interrupts when performing operations in a virtualized environment,causing the CPU to frequently switch between the Root mode and the Non-Root mode,which brings huge system performance overhead and affects the operational performance of SR-IOV cryptographic device.Aiming at this problem,the I/O interrupt of SR-IOV cryptographic device was analyzed,and a M/M/1 queuing model according to the cryptographic task first-come-first-served rules was constructed.What’s more,the key factors affecting system performance were analyzed,and the validity of the model via simulation and experiment was verified,and finally the system performance was tested.The results show that the model can quantitatively analyze the impact of the interrupt frequency on the interrupt response time and system queue length. |
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| ISSN: | 2096-109X |