An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing
As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to ass...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/564704 |
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| _version_ | 1841524691263553536 |
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| author | Andrew G. Schmidt William V. Kritikos Shanyuan Gao Ron Sass |
| author_facet | Andrew G. Schmidt William V. Kritikos Shanyuan Gao Ron Sass |
| author_sort | Andrew G. Schmidt |
| collection | DOAJ |
| description | As the number of cores per discrete integrated
circuit (IC) device grows, the importance of the network on
chip (NoC) increases. However, the body of research in
this area has focused on discrete IC devices alone which
may or may not serve the high-performance computing
community which needs to assemble many of these devices
into very large scale, parallel computing machines. This paper
describes an integrated on-chip/off-chip network that has
been implemented on an all-FPGA computing cluster. The
system supports MPI-style point-to-point messages, collectives,
and other novel communication. Results include the resource
utilization and performance (in latency and bandwidth). |
| format | Article |
| id | doaj-art-a0a401da9da0404f90c699e132e82df1 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-a0a401da9da0404f90c699e132e82df12025-02-03T05:47:35ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092012-01-01201210.1155/2012/564704564704An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable ComputingAndrew G. Schmidt0William V. Kritikos1Shanyuan Gao2Ron Sass3Information Sciences Institute, University of Southern California, 3811 North Fairfax Drive, Suite 200, Arlington, VA 22203, USAReconfigurable Computing Systems Lab, UNC Charlotte, Electrical and Computer Engineering Department, 9201 University City Boulevard, Charlotte, NC 28223, USAReconfigurable Computing Systems Lab, UNC Charlotte, Electrical and Computer Engineering Department, 9201 University City Boulevard, Charlotte, NC 28223, USAReconfigurable Computing Systems Lab, UNC Charlotte, Electrical and Computer Engineering Department, 9201 University City Boulevard, Charlotte, NC 28223, USAAs the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster. The system supports MPI-style point-to-point messages, collectives, and other novel communication. Results include the resource utilization and performance (in latency and bandwidth).http://dx.doi.org/10.1155/2012/564704 |
| spellingShingle | Andrew G. Schmidt William V. Kritikos Shanyuan Gao Ron Sass An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing International Journal of Reconfigurable Computing |
| title | An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing |
| title_full | An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing |
| title_fullStr | An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing |
| title_full_unstemmed | An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing |
| title_short | An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing |
| title_sort | evaluation of an integrated on chip off chip network for high performance reconfigurable computing |
| url | http://dx.doi.org/10.1155/2012/564704 |
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