An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing
As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to ass...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/564704 |
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| Summary: | As the number of cores per discrete integrated
circuit (IC) device grows, the importance of the network on
chip (NoC) increases. However, the body of research in
this area has focused on discrete IC devices alone which
may or may not serve the high-performance computing
community which needs to assemble many of these devices
into very large scale, parallel computing machines. This paper
describes an integrated on-chip/off-chip network that has
been implemented on an all-FPGA computing cluster. The
system supports MPI-style point-to-point messages, collectives,
and other novel communication. Results include the resource
utilization and performance (in latency and bandwidth). |
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| ISSN: | 1687-7195 1687-7209 |