TSC-IBR: A Variant of Interval-Based Memory Reclamation Using CPU’s Time-Stamp Counter
Hardware timestamps are increasingly used in concurrent data structures. On the x86_64 platform, a clock with cycle-level resolution maintained by the CPU’s time-stamp counter register is frequently employed to implement parallel algorithms, and its value can be accessed swiftly without a...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11000280/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|