Efficient implementation scheme of SM4 algorithm based on FPGA
To address the inefficient data processing performance and excessive resource utilization issues that field-programmable gate array (FPGA)-based SM4 implementations faced, an implementation scheme that adopted both iteration and pipeline in order to reduce resource consumption and improve throughput...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | zho |
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Editorial Department of Journal on Communications
2024-05-01
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| Series: | Tongxin xuebao |
| Subjects: | |
| Online Access: | http://www.joconline.com.cn/zh/article/doi/10.11959/j.issn.1000-436x.2024053/ |
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| _version_ | 1841539219032375296 |
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| author | ZHANG Hongke YUAN Haonan DING Wenxiu YAN Zheng LI Bin LIANG Dong |
| author_facet | ZHANG Hongke YUAN Haonan DING Wenxiu YAN Zheng LI Bin LIANG Dong |
| author_sort | ZHANG Hongke |
| collection | DOAJ |
| description | To address the inefficient data processing performance and excessive resource utilization issues that field-programmable gate array (FPGA)-based SM4 implementations faced, an implementation scheme that adopted both iteration and pipeline in order to reduce resource consumption and improve throughput was proposed. A combination of cyclic key extension and 32 bit pipeline encryption and decryption architecture was adopted by the proposed scheme. The cyclic key extension reduced logical resource consumption, while the 32 bit pipeline encryption and decryption improved data throughput. Additionally, an algebraic S-box that combined linear operations to select an optimal matrix from those generated by different irreducible polynomials was employed. Resource usage and computation overhead was further minimized, thus achieving an increased engineering frequency. Experimental results demonstrate a 43% throughput improvement and a 10% reduction in resource usage compared to the current best scheme. |
| format | Article |
| id | doaj-art-9db6ef0fd50f43198f057ab3970f6fd4 |
| institution | Kabale University |
| issn | 1000-436X |
| language | zho |
| publishDate | 2024-05-01 |
| publisher | Editorial Department of Journal on Communications |
| record_format | Article |
| series | Tongxin xuebao |
| spelling | doaj-art-9db6ef0fd50f43198f057ab3970f6fd42025-01-14T07:24:20ZzhoEditorial Department of Journal on CommunicationsTongxin xuebao1000-436X2024-05-014514015062276488Efficient implementation scheme of SM4 algorithm based on FPGAZHANG HongkeYUAN HaonanDING WenxiuYAN ZhengLI BinLIANG DongTo address the inefficient data processing performance and excessive resource utilization issues that field-programmable gate array (FPGA)-based SM4 implementations faced, an implementation scheme that adopted both iteration and pipeline in order to reduce resource consumption and improve throughput was proposed. A combination of cyclic key extension and 32 bit pipeline encryption and decryption architecture was adopted by the proposed scheme. The cyclic key extension reduced logical resource consumption, while the 32 bit pipeline encryption and decryption improved data throughput. Additionally, an algebraic S-box that combined linear operations to select an optimal matrix from those generated by different irreducible polynomials was employed. Resource usage and computation overhead was further minimized, thus achieving an increased engineering frequency. Experimental results demonstrate a 43% throughput improvement and a 10% reduction in resource usage compared to the current best scheme.http://www.joconline.com.cn/zh/article/doi/10.11959/j.issn.1000-436x.2024053/SM4 algorithmFPGA implementationpipeline architecturealgebraic S-box |
| spellingShingle | ZHANG Hongke YUAN Haonan DING Wenxiu YAN Zheng LI Bin LIANG Dong Efficient implementation scheme of SM4 algorithm based on FPGA Tongxin xuebao SM4 algorithm FPGA implementation pipeline architecture algebraic S-box |
| title | Efficient implementation scheme of SM4 algorithm based on FPGA |
| title_full | Efficient implementation scheme of SM4 algorithm based on FPGA |
| title_fullStr | Efficient implementation scheme of SM4 algorithm based on FPGA |
| title_full_unstemmed | Efficient implementation scheme of SM4 algorithm based on FPGA |
| title_short | Efficient implementation scheme of SM4 algorithm based on FPGA |
| title_sort | efficient implementation scheme of sm4 algorithm based on fpga |
| topic | SM4 algorithm FPGA implementation pipeline architecture algebraic S-box |
| url | http://www.joconline.com.cn/zh/article/doi/10.11959/j.issn.1000-436x.2024053/ |
| work_keys_str_mv | AT zhanghongke efficientimplementationschemeofsm4algorithmbasedonfpga AT yuanhaonan efficientimplementationschemeofsm4algorithmbasedonfpga AT dingwenxiu efficientimplementationschemeofsm4algorithmbasedonfpga AT yanzheng efficientimplementationschemeofsm4algorithmbasedonfpga AT libin efficientimplementationschemeofsm4algorithmbasedonfpga AT liangdong efficientimplementationschemeofsm4algorithmbasedonfpga |