Utilizing MRAMs With Low Resistance and Limited Dynamic Range for Efficient MAC Accelerator - Sateesh; Kaustubh Chakarwar; Shubham Sahay (IEEE Open Journal of Nanotechnology)
The recent advancements in data mining, machine learning algorithms and cognitive systems have necessitated the development of neuromorphic processing engines which may enable resource and computationally intensive applications on the internet-of-Things (IoT) edge devices with unprecedented energy efficiency. Spintronics based magnetic memory devices can emulate synaptic behavior efficiently and are hailed as one of the most promising candidates for realizing compact and ultra-energy efficient neural network accelerators. Although ultra-dense magnetic memories with multi-bit capability (MLC) were proposed recently, their application in hybrid CMOS-non-volatile memory accelerators is limited due to their low dynamic range (memory window) and high cell currents (ON/OFF-state resistance in ∼kΩ). In this work, we propose a novel supercell to enable the use of MLC MRAMs for neuromorphic multiply-accumulate (MAC) accelerators. For proof-of-concept demonstration, we exploit an MLC MRAM based on c-MTJ for realizing a highly scalable 2-FinFET-1-MRAM supercell with large dynamic range, low supercell currents and high endurance. Furthermore, we perform a comprehensive design exploration of a time-domain MAC accelerator utilizing the proposed supercell. Our detailed analysis using the ASAP7 PDK from ARM for FinFETs and an experimentally calibrated compact model for c-MTJ-based MRAM indicates the possibility of realizing a significantly high energy-efficiency of 87.4 TOPS/W and a throughput of 2.5 TOPS for a 200×200 MAC operation with 4-bit precision.