Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications
Recently, three-dimensional FLASH memory with multi-level cell characteristics has attracted increasing attention to enhance the capabilities of artificial intelligence (AI) by leveraging computingin-memory (CIM) systems. The focus is to maximize the computing performance and design FLASH memory sui...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10778276/ |
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| author | Jung Rae Cho Donghyun Ryu Donguk Kim Wonjung Kim Yeonwoo Kim Changwook Kim Yoon Kim Myounggon Kang Jiyong Woo Dae Hwan Kim |
| author_facet | Jung Rae Cho Donghyun Ryu Donguk Kim Wonjung Kim Yeonwoo Kim Changwook Kim Yoon Kim Myounggon Kang Jiyong Woo Dae Hwan Kim |
| author_sort | Jung Rae Cho |
| collection | DOAJ |
| description | Recently, three-dimensional FLASH memory with multi-level cell characteristics has attracted increasing attention to enhance the capabilities of artificial intelligence (AI) by leveraging computingin-memory (CIM) systems. The focus is to maximize the computing performance and design FLASH memory suitable for various AI algorithms, where the memory must achieve a highly controllable multi-level threshold voltage (VT). Therefore, we developed a SPICE compact model that can rapidly simulate charge trap FLASH cells for CIM to identify optimal programming conditions. SPICE simulation results of the transfer characteristics are in good agreement with the results of experimentally fabricated FLASH memory, showing a low error rate of 10%. The model was also validated against the results obtained from the TCAD tool, showing that a consistent VT change was computed in a shorter time than that required using TCAD. Then, the developed model was used to comprehensively investigate how single or multiple gate voltage (VG) pulses affect VT. Moreover, considering recent FLASH memory fabrication processes, we found that grain boundaries in polycrystalline silicon channel materials can be involved in deteriorating gate controllability. Therefore, optimizing the pulse scheme by correcting potential errors identified in advance through fast SPICE simulation can enable the accurate achievement of the specific analog states of the FLASH cells of the CIM architecture, boosting computing performance. |
| format | Article |
| id | doaj-art-84b9e31d29264ed8bef631101160da46 |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-84b9e31d29264ed8bef631101160da462025-01-10T00:00:38ZengIEEEIEEE Journal of the Electron Devices Society2168-67342025-01-01131710.1109/JEDS.2024.351158110778276Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory ApplicationsJung Rae Cho0https://orcid.org/0009-0002-6752-6122Donghyun Ryu1https://orcid.org/0000-0002-5800-7251Donguk Kim2Wonjung Kim3Yeonwoo Kim4https://orcid.org/0000-0003-2653-6375Changwook Kim5https://orcid.org/0000-0001-8992-6923Yoon Kim6https://orcid.org/0000-0002-4837-8411Myounggon Kang7https://orcid.org/0000-0003-4132-0038Jiyong Woo8https://orcid.org/0000-0002-4968-6985Dae Hwan Kim9https://orcid.org/0000-0003-2567-4012School of Electrical Engineering, Kookmin University, Seoul, South KoreaDepartment of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaSchool of Electrical Engineering, Kookmin University, Seoul, South KoreaSchool of Electrical Engineering, Kookmin University, Seoul, South KoreaDepartment of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaSchool of Electrical Engineering, Kookmin University, Seoul, South KoreaSchool of Electrical and Computer Engineering, University of Seoul, Seoul, South KoreaSchool of Advanced Fusion Studies, University of Seoul, Seoul, South KoreaSchool of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South KoreaSchool of Electrical Engineering, Kookmin University, Seoul, South KoreaRecently, three-dimensional FLASH memory with multi-level cell characteristics has attracted increasing attention to enhance the capabilities of artificial intelligence (AI) by leveraging computingin-memory (CIM) systems. The focus is to maximize the computing performance and design FLASH memory suitable for various AI algorithms, where the memory must achieve a highly controllable multi-level threshold voltage (VT). Therefore, we developed a SPICE compact model that can rapidly simulate charge trap FLASH cells for CIM to identify optimal programming conditions. SPICE simulation results of the transfer characteristics are in good agreement with the results of experimentally fabricated FLASH memory, showing a low error rate of 10%. The model was also validated against the results obtained from the TCAD tool, showing that a consistent VT change was computed in a shorter time than that required using TCAD. Then, the developed model was used to comprehensively investigate how single or multiple gate voltage (VG) pulses affect VT. Moreover, considering recent FLASH memory fabrication processes, we found that grain boundaries in polycrystalline silicon channel materials can be involved in deteriorating gate controllability. Therefore, optimizing the pulse scheme by correcting potential errors identified in advance through fast SPICE simulation can enable the accurate achievement of the specific analog states of the FLASH cells of the CIM architecture, boosting computing performance.https://ieeexplore.ieee.org/document/10778276/FLASHin-memory computingSPICE modeling |
| spellingShingle | Jung Rae Cho Donghyun Ryu Donguk Kim Wonjung Kim Yeonwoo Kim Changwook Kim Yoon Kim Myounggon Kang Jiyong Woo Dae Hwan Kim Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications IEEE Journal of the Electron Devices Society FLASH in-memory computing SPICE modeling |
| title | Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications |
| title_full | Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications |
| title_fullStr | Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications |
| title_full_unstemmed | Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications |
| title_short | Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications |
| title_sort | physics based spice compatible compact model of flash memory with poly si channel for computing in memory applications |
| topic | FLASH in-memory computing SPICE modeling |
| url | https://ieeexplore.ieee.org/document/10778276/ |
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