A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms
Prototyping using multi-FPGA platforms is unique because of its use in real-world testing and cycle-accurate information on the design. However, this is a complex and time-consuming process with multiple sub-steps. Among its sub-steps, inter-FPGA routing is the one that can take a significant percen...
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MDPI AG
2024-12-01
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| author | Umer Farooq Habib Mehrez Najam Ul Hasan |
| author_facet | Umer Farooq Habib Mehrez Najam Ul Hasan |
| author_sort | Umer Farooq |
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| description | Prototyping using multi-FPGA platforms is unique because of its use in real-world testing and cycle-accurate information on the design. However, this is a complex and time-consuming process with multiple sub-steps. Among its sub-steps, inter-FPGA routing is the one that can take a significant percentage of total prototyping time. The share of inter-FPGA routing is projected to increase further over time with the ever-increasing complexity of the target designs. In this work, we propose to integrate a Reinforcement Learning (RL)-based framework to speed up the inter-FPGA routing process. For this purpose, we first find a trade-off between the exploration and exploitation approach (also termed as the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>ϵ</mi></semantics></math></inline-formula>-greedy approach) in our RL-based framework while not affecting the final Quality of Results (QoR). To gauge its effectiveness, we then perform an extensive comparison between the proposed framework and established routing approaches. In this regard, a set of fourteen complex benchmarks is used, and the results of the proposed framework are compared against existing routability- and timing-driven routing approaches. Experimental results reveal that, on average, the proposed RL-based framework speeds up the inter-FPGA routing process by 45% and 32%, compared to routability- and timing-driven routing approaches, respectively. The speedup at the routing step further leads to an overall speedup of the backend flow by 22% and 15%, respectively. |
| format | Article |
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| institution | Kabale University |
| issn | 1424-8220 |
| language | English |
| publishDate | 2024-12-01 |
| publisher | MDPI AG |
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| spelling | doaj-art-827d4129828641bc958905413510faab2025-01-10T13:20:39ZengMDPI AGSensors1424-82202024-12-012514210.3390/s25010042A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA PlatformsUmer Farooq0Habib Mehrez1Najam Ul Hasan2School of Computer Science and Engineering, University of Sunderland, Sunderland SR6 0DD, UKLiP6 Laboratory, Sorbonne Universite, 75005 Paris, FranceSchool of Computing and Digital Technologies, Sheffield Hallam University, Sheffield S1 1WB, UKPrototyping using multi-FPGA platforms is unique because of its use in real-world testing and cycle-accurate information on the design. However, this is a complex and time-consuming process with multiple sub-steps. Among its sub-steps, inter-FPGA routing is the one that can take a significant percentage of total prototyping time. The share of inter-FPGA routing is projected to increase further over time with the ever-increasing complexity of the target designs. In this work, we propose to integrate a Reinforcement Learning (RL)-based framework to speed up the inter-FPGA routing process. For this purpose, we first find a trade-off between the exploration and exploitation approach (also termed as the <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>ϵ</mi></semantics></math></inline-formula>-greedy approach) in our RL-based framework while not affecting the final Quality of Results (QoR). To gauge its effectiveness, we then perform an extensive comparison between the proposed framework and established routing approaches. In this regard, a set of fourteen complex benchmarks is used, and the results of the proposed framework are compared against existing routability- and timing-driven routing approaches. Experimental results reveal that, on average, the proposed RL-based framework speeds up the inter-FPGA routing process by 45% and 32%, compared to routability- and timing-driven routing approaches, respectively. The speedup at the routing step further leads to an overall speedup of the backend flow by 22% and 15%, respectively.https://www.mdpi.com/1424-8220/25/1/42reinforcement learningprototypingmulti-FPGA platformsbackend flowinter-FPGA routing |
| spellingShingle | Umer Farooq Habib Mehrez Najam Ul Hasan A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms Sensors reinforcement learning prototyping multi-FPGA platforms backend flow inter-FPGA routing |
| title | A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms |
| title_full | A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms |
| title_fullStr | A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms |
| title_full_unstemmed | A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms |
| title_short | A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms |
| title_sort | reinforcement learning based approach for efficient routing in multi fpga platforms |
| topic | reinforcement learning prototyping multi-FPGA platforms backend flow inter-FPGA routing |
| url | https://www.mdpi.com/1424-8220/25/1/42 |
| work_keys_str_mv | AT umerfarooq areinforcementlearningbasedapproachforefficientroutinginmultifpgaplatforms AT habibmehrez areinforcementlearningbasedapproachforefficientroutinginmultifpgaplatforms AT najamulhasan areinforcementlearningbasedapproachforefficientroutinginmultifpgaplatforms AT umerfarooq reinforcementlearningbasedapproachforefficientroutinginmultifpgaplatforms AT habibmehrez reinforcementlearningbasedapproachforefficientroutinginmultifpgaplatforms AT najamulhasan reinforcementlearningbasedapproachforefficientroutinginmultifpgaplatforms |