APA (7th ed.) Citation

Alawneh, T. A., Sharadqh, A. A. M., Sharah, A. A., Awada, E., Alkasassbeh, J. S., Al-Rawashdeh, A. Y., & Al-Qaisi, A. A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems. IEEE.

Chicago Style (17th ed.) Citation

Alawneh, Tareq A., Ahmed A. M. Sharadqh, Ashraf Al Sharah, Emad Awada, Jawdat S. Alkasassbeh, Ayman Y. Al-Rawashdeh, and Aws Al-Qaisi. A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems. IEEE.

MLA (9th ed.) Citation

Alawneh, Tareq A., et al. A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems. IEEE.