RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training
This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/10772713/ |
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| author | Andrew Maclellan Louise H. Crockett Robert W. Stewart |
| author_facet | Andrew Maclellan Louise H. Crockett Robert W. Stewart |
| author_sort | Andrew Maclellan |
| collection | DOAJ |
| description | This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver. |
| format | Article |
| id | doaj-art-7b1c9f4604d64e1c85c4e99ff4074915 |
| institution | Kabale University |
| issn | 2644-1225 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-7b1c9f4604d64e1c85c4e99ff40749152025-01-10T00:03:48ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252025-01-016384910.1109/OJCAS.2024.350962710772713RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware TrainingAndrew Maclellan0https://orcid.org/0000-0001-9624-2212Louise H. Crockett1https://orcid.org/0000-0003-4436-0254Robert W. Stewart2https://orcid.org/0000-0002-7779-8597Department of Electronic and Electrical Engineering, StrathSDR, University of Strathclyde, Glasgow, U.K.Department of Electronic and Electrical Engineering, StrathSDR, University of Strathclyde, Glasgow, U.K.Department of Electronic and Electrical Engineering, StrathSDR, University of Strathclyde, Glasgow, U.K.This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD’s RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver.https://ieeexplore.ieee.org/document/10772713/Deep learning (DL)wireless communicationsAMDFPGARFSoCPYNQ |
| spellingShingle | Andrew Maclellan Louise H. Crockett Robert W. Stewart RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training IEEE Open Journal of Circuits and Systems Deep learning (DL) wireless communications AMD FPGA RFSoC PYNQ |
| title | RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training |
| title_full | RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training |
| title_fullStr | RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training |
| title_full_unstemmed | RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training |
| title_short | RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training |
| title_sort | rfsoc modulation classification with streaming cnn data set generation x0026 quantized aware training |
| topic | Deep learning (DL) wireless communications AMD FPGA RFSoC PYNQ |
| url | https://ieeexplore.ieee.org/document/10772713/ |
| work_keys_str_mv | AT andrewmaclellan rfsocmodulationclassificationwithstreamingcnndatasetgenerationx0026quantizedawaretraining AT louisehcrockett rfsocmodulationclassificationwithstreamingcnndatasetgenerationx0026quantizedawaretraining AT robertwstewart rfsocmodulationclassificationwithstreamingcnndatasetgenerationx0026quantizedawaretraining |